8 Bipolar Transistors

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8 Bipolar Transistors
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Small-signal NPN

• Variations of standard Bipolar -- When
  single-level Metal M1 only -- stretching
  terminals to allow one or more leads to route
  between terminals

Stretched-terminal Transistor
Stretched-Collector
Stretched-Base
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• Upgrading NPN gt tries to increase EBJ area for
  higher Beta
• problem - pinched Base leads to high RB
  - Emitter crowding !
• OK for High b, Moderate Speed

4

• Layout to reduce RB (for higher speed)
• but also reduces BETA (due to small
  Area/Periphery ratio)

C
B E B E B E B

• double-Base reduces RB to about 0.25 RB

• superior freq. response,
• inferior b

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Substrate PNP -- in standard Bipolar

• lacks full isolation

P
N
P
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• NPN
• Doping level
• Emitter diffusion 1020 cm-3
• 10 Ohm
• Base diffusion 1017 cm-3
• typical b 150 (_at_ 0.8mA/mm2)

• Substrate PNP
• Doping level
• Emitter (Base diffusion of NPN) 1017 cm-3
• 100 Ohm
• Base (Nepi doping) much lower
• typical b 30 (_at_ 30mA/mm2)
• typical Ic 1 - 2 mA
• not practical for high current PNP !

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Higher-current substrate PNP
E 25 mm wide Not to be wider than 25-50 mm
because of pinched sheet 10kW/sq. under Emitter.
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Lateral PNP in standard Bipolar

• not much can do to boost Switching speed
• Beta can be improved by layout.
• Narrower Base Width gt higher Beta, lower VA
• Wider Base Width gt lower Beta, larger VA
• b VA const. Approximately.

• b depends on
• g emitter injection efficiency
• NB base doping
• tB base recombination

• WB Base width
• Collection efficiency ? under Layout
  designers control.

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Lateral PNP in standard Bipolar
Drawn width
Actual width
Pbase
Pbase
Pbase
E
C
C
Effective width
B
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Constructing Lateral PNP
Example layout -- basic
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Example Split-Collector Lateral PNP
C
C
1/4-1/4-1/4-1/4
1/2-1/2
1/6-1/6-1/6-1/4-1/4
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Current Mirror using Split-Collector Lateral PNP
Simplified Schematic circuit
Q1A
1/2
E
Q1B
1/2
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• Collector-Ring Circular vs. Square
• Circular
• Base width well defined and shorter
• Good Area/Periphery ratio
• Difficult to layout
• Square
• Base width longer due to longer diagonal path
• Poor Area/Periphery ratio
• Easier Layout

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Example hot-dog transistor, arrayed-emitter
transistor

• current is proportional to the of emitters
• hexagonal packing for small area

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ALTERNATIVE SMALL-SIGNAL BIPOLAR TRANSISTORS

• (1) Extensions to Standard Bipolar
• Super-b NPN gt low input current diff pair
  for opamp
• deep-P PNP

• Deep Emitter diff gt small WB lt0.1mm
• Beta gt 5000 !
• Punch-thru at 1-3 Volts VA 1-3Volts

Super-b NPN
Standard Bipolar
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• deep-P PNP

Standard Bipolar lateral PNP
Deep-P lateral PNP

• Improved emitter injection
• deep diff gt larger fraction of minority
  injection from the
  sidewalls ! gt 2-3times higher current density
• high current Beta rolloff at
  200-500mA in deep-P laterals versus 100-200mA
  in pBase laterals.

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Layout of CMOS Substrate PNP

• Thinner Source-Drain regions (a CMOS trend)is
  accompanied of reduced gains ? because of metal
  contacts in close proximityof PN junctions.
• Carriers when reach metal contacts recombine
  instantaneously ? which steepens
  minoritycarrier concentration profile in
  Emitter, thusreduces g injection
  efficiencyIEp/(IEnIEp)

• Place small contacts far away from the edge.

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Layout of Lateral PNP in NWell CMOS

• Field plate Poly ? PolyVE, No PMOS channel
  in Base
• PSD for E and C self-align to Poly plate ?
  very short WB

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Layout of Shallow Well NPN in CMOS

• Two types of CMOS Transistor
• lower V Tr for core logic, ex) 5V
• higher V Tr for analog and interface, ex) 15V
• multiple Wells. Shallow, heavy doping low V
• Deep Nwellhigh V PMOS
• Shallow Nwelllow V PMOS
• Shallow Pwelllow V NMOS
• CDI NPN using Shallow Pwell
• Large bgt100, lower VA
• Punchthru problem (C total depletion)

SPwell thin, lightly doped
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IC-VCE Characteristic With or W/O DeepN NBL
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(2) Analog BiCMOS
- Standard Bipolar N-type (111) epi - BiCMOS
P-type (100) epi gt Nwell, graded diffusion
higher resistivity for N-collector gt if no
deep-N sinker, then soft transition
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(2) Analog BiCMOS
- CDI NPN - (collector diffused isolation)
(standard bipolar NPN)
gt Vop is limited to 15-20V due to shallow NWell
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(2) Analog BiCMOS

• Extended-Base NPN for higher VCEO 40-60V
• at the expense of poor VA and reducedsafe
  operating area.

• Base pBase pEpi
• Collector NBL. There is no NWell
• lower VA, reduced Gummel number

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(4) Advanced Bipolars

• Fast BJT (control saturation, junction Cap, base
  R, and base transit time tt)
• Special, reduced EBJ area NPN Washed-emitter NPN

? Eliminates overlap of Emitter diff of emitter
contact
Washed-Emitter NPN
Conventional diffused NPN
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(4) Advanced Bipolars

• - Polysilicon Emitter
• much thinner, precisely controlled
• emitter diffusions than Washed-emitter

gt Betas up to six times greater
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- Oxide Isolated Transistors
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- Oxide Isolated Transistors

• Modern processes replace LOCOS by STI (shallow
  trench iso)
• Too large distance between Base contact and
  Emitter
• increases RB and CBC

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- Oxide Isolated Transistors

• Ppoly contacts Base
• Npoly contacts Emitter
• Reduces E to B distance

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- Oxide Isolated Transistors
Fab Steps
?
?

• high-Energy N-type implant (SIC)

?

• brief, high-T anneal causes Boron to diffuse
  fromP-poly to underlying Nwell, turn Nwell Si to
  p-Si(Extrinsic Base).

SICself-aligned Implanted subcollector
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• SiGe Transistor
• SiGe HBT can have over 50 GHz

- Fast(high speed) BJT double-poly
self-aligned SiGe fast tB(base transit time),
high b, high VA.
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• SiGe Transistor
• SiGe HBT can have over 50 GHz

- High energy implant forself-aligned
sub-collector
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• SiGe Transistor
• SiGe HBT can have over 50 GHz

• B-doped SiGe (epi)
• oxide/nitride on top

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• SiGe Transistor
• SiGe HBT can have over 50 GHz

• Etch Emitter window thru oxide/nitride stack
• As-doped npoly deposited into window as Emitter

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• SiGe Transistor
• SiGe HBT can have over 50 GHz

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SiGe HBT
Table 1 Comparison of CMOS with conventional and
SiGe BJTs (After Harame)
SiGe Base is graded for higher E-field, And
faster Base Transit ? higher fT
SiGe HBT cross-section