ECE 491 Senior Design I

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ECE 491 - Senior Design I

• Lecture 9 - Data Communications 2, Discuss Lab 4
• Fall 2004

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Where we are

• Last Time
• Feedback from Lab 2
• Network Protocols - Overview
• Data Communication
• Asynchronous Serial Communication (RS-232)
• Discuss Lab 3
• Today
• Data Communication
• Asynchronous Serial Communication (RS-232)
• Manchester Codes
• Discuss Lab 4
• More about Verilog-Based Design

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Lab 3 - RS-232 Transmitter
Transmitter
DATA
START
TxD
READY
CLK
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Lab 3 Design Ideas

• Assume clock rate baud rate
• Use a 10-bit shift register
• Start bit (always 0)
• Data (8 bits)
• Stop bit (always 1)
• General Operation
• Load when START1
• Stop shifting when shift register 0000000001

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Other Lab 3 Tasks

• Build a testbench to test the design (use
  Verilogger to simulate if you like it better)
• Build a clock divider to create a 9600Hz clock
  from the 50MHz clock on the S3 board.
• Modify s3board.v to instantiate your transmitter
  with data connected to slide switches, start
  connected to pushbutton (debounce pushbutton if
  necessary)
• Test on S3 board with serial cable and
  HyperTerminal on PC

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Debugging Lab 3

• Make sure txd output constraint is un-commented
• Double-Check the Code
• Double-Check the Simulation
• Check outputs on the oscillocope
• Add output ports for
• Transmitter Clock
• READY
• TxD (copy)
• Constrain using pins connected to A2 Connector

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Detail - A2 Expansion Connector
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Debugging with the Oscillocope

• Transmitter Clock - is frequency right?
• READY - Does it appear while START is pressed?
• TxD (copy) - is the value correct?
• Use READY to sync the scope while START is
  pressed
• Watch transmitted waveform - is it what is
  expected?

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Lab 4 - Receiver Design
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Recever Design - Challenges

• Sender and Recever are not synchronized (they
  run off separate clocks)
• But, the transmission rate is known and fixed

S
R
SCLK
RCLK
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Receiver Design - General Approach

• Clock receiver at a fixed multiple of data rate
  (16x)
• Use falling edge of start bit to synchronize and
  then
• Delay to middle of start bit and check (ignore
  spurious start bits)
• Delay to middle of each data bit and sample
• Delay to middle of stop bit and check(framing
  error if stop bit ? 1)

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Receiver Design - General Approach

• Use shift register to convert serial - parallel
• Use counters to calculate delay values
• Use a Finite State Machine as control unit

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Lab 4 - Additional Tasks

• Verify using a testbench that
• Produces input from behavioral code AND
• Produces input using Lab 3s transmitter module
• Add a clock divider
• Add to s3board.v
• Tie data output to seven-segment displays
• Tie READY, FERR to LEDs
• Connect rxd to RS-232 input
• Include a RESET tied to a pushbutton
• Comple complete design, download, and test using
  HyperTerminal

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Review - Verilog-based Design

• Key idea think in terms of hardware first
• Combinational Logic
• Sequential Logic
• State Machines
• Then, write code using standard templates
• Combinational Logic
• Continuous assignment
• Always blocks (combinational)
• Sequential Logic
• Clocked always blocks
• State Machines
• Sequential always block for state register AND
• Combinational always block for next state /
  output logic

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Review - Continuous Assignment

• General Form
• assign wire expression
• Example
• module fulladder(a, b, cin, sum, cout)
• input a, b, cin
• output sum, cout
• assign sum a b cin
• assign cout a b a cin b cin
• endmodule

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Review - Combinational always blocks

• Motivation
• assign statements are fine for simple functions
• More complex functions require procedural
  modeling
• Basic syntax
• always (input1 or input2 or ...)
• statement
• or
• always (input1 or input2 or ...) )
• begin
• statement-sequence
• end

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Combinational Modeling with always

• Example 4-input mux behavioral model
• module mux4(d0, d1, d2, d3, s, y)
• input d0, d1, d2, d3
• input 10 s
• output y
• reg y
• always _at_(d0 or d1 or d2 or d3 or s)
• case (s)
• 2'd0 y d0
• 2'd1 y d1
• 2'd2 y d2
• 2'd3 y d3
• default y 1'bx
• endcase
• Endmodule

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More about always

• Specifies logic with procedural statements
• Simulation model executes statements in order
• Synthesized hardware matches simulation
• reg declarations
• treat like variables in C or Java
• assignment holds value until a new assignment is
  made
• module my_logic(a, b, c, d)
• input a, b
• output c, d
• reg c,d
• always _at_(a or b) begin
• c a b
• d b c
• end
• endmodule

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Review - Data Types and Module Ports

• Input ports must always be a wire (net)
• Output ports can be wire or reg

wire
reg
wire
wire
wire
wire
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Synthesizing Comb. Logic - if without else
(latch inference)

• if without else output depends on previous value
• always _at_(a or x or y) begin
• if (a 1b1) w x
• end
• What if no previous value is specified?
• Must preserve the semantics of the language
• This requires a latch inference to store old
  value

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Synthesizing Comb. Logic - case statements

• Verilog case treated as if / else if / else ...
• always _at_(e or x or y) begin
• case (e)
• 2b00 w x y
• 2b01 w x - y
• 2b10 w x y
• default w 4b0000
• endcase
• end
• Use default to avoid latch inference!

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Synthesizing Comb. Logic -One Last Pitfall

• always must include all inputs in sensitivity
  list
• OR mismatch between synthesis simulation!
• always _at_(e or x) begin
• case (e)
• 2b00 w x y
• 2b01 w x - y
• 2b10 w x y
• default w 4b0000
• endcase
• end

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Sequential Design in Verilog - Basic Constructs

• Describe edge-triggered behavior using
• always block withedge event
• always _at_(posedge clock-signal)
• always _at_(negedge clock-signal)
• Nonblocking assignments (lt)
• _at_always(posedge clock-signal)
• begin
• output1 lt expression1
• . . .
• output2 lt expression2
• . . .
• end

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Combining Sequential and Combinational Outputs

• General circuit - both registered and comb.
  outputs
• Approach multiple always blocks

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Example Adding carry to 4-bit Counter

• module counter(clk, Q, carry)
• input clk
• output 30 Q
• output carry
• reg 30 Q // a signal that is assigned a
  value
• assign carry (Q 4'b1111)
• always _at_( posedge clk )
• begin
• Q lt Q 1
• end
• endmodule

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Review - State Transition Table

• Transition List - lists edges in STD
• PS Condition NS Output
• IDLE ARM' DOOR' IDLE 0
• IDLE ARMDOOR BEEP 0
• BEEP ARM WAIT 1
• BEEP ARM' IDLE 1
• WAIT ARM BEEP 0
• WAIT ARM' IDLE 0

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Coding FSMs in Verilog - Explicit Style

• Clocked always block - state register
• Combinational always block -
• next state logic
• output logic

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Coding FSMs in Verilog - Code Skeleton

• Part 1 - Declarations
• module fsm(inputs, outputs)
• input . . .
• input . . .
• reg . . .
• parameter NBITS-10
• S0 2'b00
• S1 2'b01
• S2 2b'10
• S3 2b'11
• reg NBITS-1 0 CURRENT_STATE
• reg NBITS-1 0 NEXT_STATE

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Coding FSMs in Verilog - Code Skeleton

• Part 2 - State Register, Logic Specification
• always _at_(posedge clk)
• begin
• CURRENT_STATE lt NEXT_STATE
• end
• always _at_(CURRENT_STATE or xin)
• begin
• case (CURRENT_STATE)
• S0 . . . determine NEXT_STATE, outputs
• S1 . . . determine NEXT_STATE, outputs
• end case
• end // always
• endmodule

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FSM Example - Car Alarm

• Part 1 - Declarations, State Register
• module car_alarm (arm, door, reset, clk, honk )
• input arm, door, reset, clk
• output honk
• reg honk
• parameter IDLE0,BEEP1,HWAIT2
• reg 10 current_state, next_state
• always _at_(posedge reset or posedge clk)
• if (reset) current_state lt IDLE
• else current_state lt next_state

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FSM Example - Car Alarm

• Part 2 - Logic Specification
• always _at_(current_state or arm or door)
• case (current_state)
• IDLE
• begin
• honk 0
• if (arm door) next_state BEEP
• else next_state IDLE
• end
• BEEP
• begin
• honk 1
• if (arm) next_state HWAIT
• else next_state IDLE
• end

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FSM Example - Car Alarm

• Part 3 - Logic Specification (contd)
• HWAIT
• begin
• honk 0
• if (arm) next_state BEEP
• else next_state IDLE
• end
• default
• begin
• honk 0
• next_state IDLE
• end
• endcase
• endmodule

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Coming Up

• More about Physical Links
• Manchester Codes

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Course Map