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General topic Interaction of FPGA-based circuits
with peripheral devices 1. Input and output. 2.
Interface of FPGA with a VGA monitor. 3.
Interface of FPGA with a keyboard. 4. Design of
arithmetical circuits. 5. Examples.
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What do we want to design?
Arithmetic block
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PS2_Keyboard entity work.Keyboard generic map
(AddressBits gt ADDRESSLENGTH) port map
( Reset gt Reset, Clock gt
ClockVGA, PS2Clock gt PS2Clock, PS2Data
gt PS2Data, ASCII gt
ASCII, WriteEnable gt WriteEnable, WriteAddre
ss gt WriteAddress)
---------- APPLICATION-SPECIFIC BLOCK B e g i
n ---------- Input from keyboard and output to
VGA RAM Arithmetic entity
work.ArithmeticBlock generic map ( AddressBits
gt ADDRESSLENGTH, StateMaxValue gt
52, NumberOfColumns gt TEXTCOLUMNS ) port
map ( ASCII_in gt ASCII, ASCII_out gt
RAMData, Address_in gt WriteAddress, Address_
out gt RAMWriteAddress, clk gt
ClockVGA, rst gt Reset, WE_in gt
WriteEnable, WE_out gt
RAMWriteEnable) ---------- APPLICATION-SPECIFIC
BLOCK E n d
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VGA_RAM entity work.RAM generic map
( AddressBits gt ADDRESSLENGTH,
DataBits gt 8) port map ( Clock
gt ClockVGA, WriteAddress gt
RAMWriteAddress, WriteEnable gt
RAMWriteEnable, DataIn gt
RAMData, ReadAddress gt ReadAddress, DataOut
gt SymbolPos)
---------- APPLICATION-SPECIFIC BLOCK B e g i
n ---------- Input from keyboard and output to
VGA RAM Arithmetic entity
work.ArithmeticBlock generic map ( AddressBits
gt ADDRESSLENGTH, StateMaxValue gt
52, NumberOfColumns gt TEXTCOLUMNS ) port
map ( ASCII_in gt ASCII, ASCII_out gt
RAMData, Address_in gt WriteAddress, Address_
out gt RAMWriteAddress, clk gt
ClockVGA, rst gt Reset, WE_in gt
WriteEnable, WE_out gt
RAMWriteEnable) ---------- APPLICATION-SPECIFIC
BLOCK E n d
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A
It is allowed to write
The character code is available for recording
1 after each key press-release
Address_out lt conv_std_logic_vector((lineNumberO
fColumns column),AddressBits)
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entity ArithmeticBlock is generic ( AddressBits
natural StateMaxValue natural
NumberOfColumns natural ) Port ( ASCII_in
in STD_LOGIC_VECTOR (7 downto 0)
ASCII_out out STD_LOGIC_VECTOR (7
downto 0) Address_in in
STD_LOGIC_VECTOR (AddressBits - 1 downto 0)
Address_out out STD_LOGIC_VECTOR
(AddressBits - 1 downto 0) clk
in STD_LOGIC rst in
STD_LOGIC WE_in in
STD_LOGIC WE_out out
STD_LOGIC ) end ArithmeticBlock
clock (clk)
reset (rst) active 1
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architecture Behavioral of ArithmeticBlock
is signal Op1 STD_LOGIC_VECTOR(7 downto 0)
-- one decimal digit in binary code signal Op2
STD_LOGIC_VECTOR(7 downto 0) -- one decimal
digit in binary code signal sum
STD_LOGIC_VECTOR(7 downto 0) -- binary signal
Difference STD_LOGIC_VECTOR(7 downto 0) --
binary signal sumMSB STD_LOGIC_VECTOR(7 downto
0) -- ASCII signal sumLSB STD_LOGIC_VECTOR(7
downto 0) -- ASCII signal DifLSB
STD_LOGIC_VECTOR(7 downto 0) -- ASCII signal
sign STD_LOGIC_VECTOR(7 downto 0) --
ASCII signal state integer range 0 to
StateMaxValue signal line, line_local
integer range 0 to 39 signal column,
column_local integer range 0 to 79 signal
ASCII_local std_logic_vector(7 downto
0) signal Operand1 string(1 to 16)
"Operand 1 " constant Operand2 string(1
to 16) "Operand 2 " constant SumR
string(1 to 16) "Sum " constant
DifR string(1 to 16) "Difference "
sum Op1 Op2 Entering Op1 and Op2 from
keyboard Difference Op1 - Op2
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Array to convert binary numbers to BCD numbers
type rom_type is array (0 to 99) of
std_logic_vector (7 downto 0) constant ROM
rom_type ("00000000","00000001","00000010",
"00000011","00000100","00000101","00000110","00000
111","00001000", "00001001", "00010000","00010001
","00010010", "00010011","00010100","00010101","00
010110","00010111","00011000", "00011001",
"00100000","00100001","00100010", "00100011","0010
0100","00100101","00100110","00100111","00101000",
"00101001", "00110000","00110001","00110010", "0
0110011","00110100","00110101","00110110","0011011
1","00111000", "00111001", "01000000","01000001",
"01000010", "01000011","01000100","01000101","0100
0110","01000111","01001000", "01001001",
"01010000","01010001","01010010", "01010011","0101
0100","01010101","01010110","01010111","01011000",
"01011001", "01100000","01100001","01100010", "0
1100011","01100100","01100101","01100110","0110011
1","01101000", "01101001", "01110000","01110001",
"01110010", "01110011","01110100","01110101","0111
0110","01110111","01111000", "01111001",
"10000000","10000001","10000010", "10000011","1000
0100","10000101","10000110","10000111","10001000",
"10001001", "10010000","10010001","10010010", "1
0010011","10010100","10010101","10010110","1001011
1","10011000", "10011001" )
An algorithm of such conversion without using
memory will be considered in practical classes
We assume that each operand is one-digit integer
decimal number, such as 0,1,2,,9. In practical
classes we will consider examples with two-digits
integer decimal numbers, such as 0,1,2,,99
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-- arithmetical operations sum and
difference sum lt ("0000"(Op1(3 downto
0)))("0000"(Op2(3 downto 0))) difference lt
("0000"(Op1(3 downto 0)))-("0000"(Op2(3 downto
0))) when ("0000"(Op1(3 downto
0)))gt("0000"(Op2(3 downto 0))) else
("0000"(Op2(3 downto 0)))-("0000"(Op1(3 downto
0))) sign lt std_logic_vector(to_unsigned(charac
ter'pos(' '), 8)) when ("0000"(Op1(3
downto 0)))gt("0000"(Op2(3 downto 0))) else
std_logic_vector(to_unsigned(character'pos('-'),
8)) sumMSB lt "0011" ROM(conv_integer(sum))(7
downto 4) sumLSB lt "0011"
ROM(conv_integer(sum))(3 downto 0) DifLSB lt
"0011" ROM(conv_integer(difference))(3 downto
0) -- taking operands from keyboard Op1 lt
"00110000" when rst '1' else ASCII_in when
((ASCII_in gt "00110000") and (ASCII_in lt
"00111001")) and (Address_in(0) '0') and
(WE_in '1') Op2 lt "00110000" when rst '1'
else ASCII_in when ((ASCII_in gt "00110000")
and (ASCII_in lt "00111001")) and
(Address_in(0) '1') and (WE_in '1')
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process(clk, rst) begin if rst '1' then state
lt 0 elsif falling_edge(clk) then if
stateStateMaxValue then statelt0 else statelt
state 1 end if end if end
process process(clk, rst) begin if rst '1'
then null elsif rising_edge(clk) then case
state is when 1 to 16 gt line_local lt
9 column_local lt 14 state ASCII_local
lt std_logic_vector(to_unsigned(character'pos(Op
erand1(state)), 8)) when 17 to 32 gt
line_local lt 10 column_local lt 14
state - 16 ASCII_local lt
std_logic_vector(to_unsigned(character'pos(Operan
d2(state-16)), 8)) when 33 gt line_local lt
9 column_local lt 14 16 3 ASCII_local
lt Op1 when 34 gt line_local lt 10
column_local lt 14 16 3 ASCII_local lt
Op2
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when 1 to 16 gt line_local lt 9 column_local
lt 14 state ASCII_local lt std_logic_vector(to_
unsigned(character'pos(Operand1(state)), 8))
signal Operand1 string(1 to 16) "Operand 1
"
Operand 1
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when 33 gt line_local lt 9 column_local lt 14
16 3 ASCII_local lt Op1
Operand 1
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when 35 to 50 gt line_local lt
11 column_local lt 14 state -
34 ASCII_local lt std_logic_vector (to_uns
igned(character'pos(SumR(state-34)), 8)) when
51 gt line_local lt 11 column_local lt 14
16 3 ASCII_local lt sumMSB when 52 gt
line_local lt 11 column_local lt 14 16
4 ASCII_local lt sumLSB when 53 to 68
gt line_local lt 12 column_local lt 14
state - 52 ASCII_local lt std_logic_vector
(to_unsigned(character'pos(DifR(state-52)),
8)) when 69 gt line_local lt
12 column_local lt 14 16
3 ASCII_local lt sign when 70 gt
line_local lt 12 column_local lt 14 16
4 ASCII_local lt DifLSB when others
gt null end case end if end
process
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Results
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Conclusion from the second class

• VHDL code allowing to enter data from a keyboard
  and to display data on a VGA monitor is reusable
  in such sense that it can be used again in
  different projects and to provide input/output
  facilities
• We can replace arithmetic block with any other
  block that requires interaction with
  keyboard/monitor VGA
• This block has to provide similar interface with
  circuits supporting interfaces with physical
  keyboard/monitor VGA
• The next example will be dedicated to the design
  of a finite state machine, which gets a binary
  vector with the size N from a keyboard and tests
  if this vector contains M succeeding ones. The
  results will be displayed on VGA screen