Custom IC Development for SNAP

1
Custom IC Development for SNAP

• Jean-Pierre Walder
• Lawrence Berkeley National Laboratory
• July 2002

2
Outline

• Introduction
• Custom ICs RD goals
• Front end readout block diagram
• SNAP IC plan
• Front end readout requirements
• Signal processing
• Front end dynamic range and resolution
• Multi slope ADC concept
• ADC architecture study
• Technology survey
• Behavior of sub micron CMOS at cold temperature
• Radiation tolerance
• Conclusion

3
Introduction

• SNAP instrument consists of CCDs and HgCdTe
  sensors for wide-field imaging and spectroscopy
  ? We have identified areas where custom
  integrated circuits are a viable solution to meet
  SNAPs requirements
• Custom ICs allow power, noise optimization
  compared to a discrete solution.
• ? We envision a readout scheme that focuses on
  CCD devices, keeping in mind the characteristics
  of the HgCdTe in case Rockwell is not sucessful.
• RD are required to mitigate technical schedule
  risk
• Sensor front-end (correlated double sampler)
• Analog-to-digital converter
• CCD controller (maybe commercial parts or custom)

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Custom ICs RD Goals

• The RD goals are to provide thorough and
  complete answers in the following areas
• Readout noisenoise optimization and signal
  processing study
• Power optimizationIn general, low power is
  required for space, and very low power is
  mandatory if we want to locate the front end
  electronics close to the CCDs. Its power
  consumption should be a small fraction of the CCD
  power.
• Operation at cold temperatureEvaluate current
  technology performances at cold temperature
  (140K) and verify/modify the model for a reliable
  design.
• Radiation hardness Evaluate current technology
  performances in radiation environment especially
  at low temperature
• PrototypeDesign and test a reliable prototype
  before construction

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Front end readout block diagram
Mixed mode front end custom IC Multi channel chip
Clocks, control
Front end IC
CCD
Analog input
Analog signal processing
ADC
Digital out
Amplification
(One channel)
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SNAP IC plan

• Implementation of a signal processing test chip
  containing
• 4 channels
• Input amplifier
• Correlated double sampling
• Integrator
• Multi gain amplifier (multi slope)
• Individual test structures
• Test transistors

• This is to verify
• Noise performance
• Power consumption
• Multi slope concept
• Operation at 140K and 300K
• Radiation tolerance

• A second iteration implementing an integrated ADC
  with a low noise front end is planned.

• This is to verify
• Noise performance
• Power consumption
• Resolution/linearity
• Sampling rate
• Electronic system noise

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Front end readout requirements

• Low noisePhotometry CCD electronic noise ?
  4e rms HgCdTe electronic
  noise ? 5e rmsSpectrograph CCD electronic
  noise ? 2e rms HgCdTe
  electronic noise ? 5e rms
• Large dynamic range96dB from noise floor to
  130ke well depth
• Readout frequency ? 100 kHz
• Radiation tolerant 10 kRad ionization (well
  shielded)
• Low power ? 200mJ/image/channel
• Operation at 140K and 300KAllow normal operation
  at 140K and chip testing at room temperature
• Compact
• Robust, space qualified

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Signal processing (1/4)
CCD output stage
Floating diffusion capacitor
Serial register
Reset FET
Output stage
Source follower
Timing
RG (reset)
(Summing Well)
SW
Output signal
Reset signal
Video signal
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Signal processing (2/4)
CCD noise sources
Thermal and 1/f noise of the output transistor
Thermal noise of the output resistor
Thermal and 1/f noise
KTC noise
Frozen noise charge, with a variance of KTC,
stored in Cfd just after reset.
Thermal noise
Signal processing is needed to reduce the CCD
noise

• Correlated double sampling ( Vsignal Vreset)
  remove the KTC and 1/f noise.
• Integration remove the thermal noise.

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Signal processing (3/4)
C (100pF)
CCD noise only
R
t
Out
X1
CCDnoisesource
(Noiseless)
Integrator
t
-X1
CCD conversion gain 3.5mV/e
Correlated Double Sampler
Integration time t
Input referred noise (e)
Out
4ms (R20KW)
2.6
t
t
8ms (R40KW)
1.86
time
1.8
10ms (R50KW)
Reset integration
Signal integration
Real integration during 2t. Good rejection of the
CCD thermal noise.
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Signal processing (4/4)
CCD noise first stage noise
C (100pF)
R
t
Out
X1
CCDnoisesource
(Noiseless)
t
-X1
CCD conversion gain 3.5mV/e
Input referred noise (e)technology A / B
Integration time t
Out
4ms (R20KW)
2.8 / 2.9
t
t
8ms (R40KW)
2.1 / 2.2
10ms (R50KW)
1.92 / 2
time
Reset integration
Signal integration
The 1/f noise of the input stage is reduced by
the CDS The thermal noise from the input stage is
negligible compared to the CCD thermal noise
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Front end dynamic range and resolution

• The dynamic range for the signal is 96dB (16
  bits)
• From 2 electrons (CCD noise) up to 130000
  electrons
• The Signal/Noise ratio of the sensor/readout
  chain is less due to the Poisson process of the
  light interacting in the sensor.
• dN/N 1/ (N)½ where N is the number of
  photons.
• The readout chain should digitize the signal with
  an LSB size which depends of the signal amplitude
  such that the quantization noise is still below
  the Poisson noise.

CCD electronic noise
Poisson
Quantization noise area
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Multi slope ADC concept
Gain 1
Digital out
Input
Signal processing
MUX
12 bits ADC
Gain 2
Gain 32
½ of (Poisson ? elec noise)
Poisson elec noise
Gain 32 quantization noise referred to the
input
Gain 1
Gain 2
The dynamic range is covered using 3 slopes and a
12 bit ADC
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ADC architecture study

• Several architecture were investigated.
• In the range of the required resolution (12 bits)
  and sampling rate (lt100kHz), we have identified
  two types
• Pipeline ADC
• Single ramp ADC

Single ramp ADC
Pipeline ADC (1 bit cell)
X m

S/H
X2
Input
Digital out
Input
-
X nb of bits
cmp
Digital
DAC
ADC
Ramp
Counter
Digital out (1 bit)
Sampling rate ltlt Clock frequency Number of stage
1 Multi channel one ramp generator could
supply m comparators.
Sampling rate Clock frequency Number of stages
number of bits
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Technology survey

• 10 commercial CMOS sub micron processes where
  investigated.
• Selection criteria
• Noise
• Matching, precision
• Transistor performances
• Passive components availability and precision
• Expected production life time
• Radiation tolerance

Technologies studied for noise and power
performance
Minimum feature size
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Behavior of sub micron CMOS at cold temperature
One option is to locate the front end readout IC
close to the CCD. But, the operating temperature
then will be 140K. Does deep submicron technology
work at 140K?
Several studies of sub micron CMOS operating at
temperatures ranging from 77K to 300K have been
done and are reported in the literature (IEEE
transactions on electron devices).

• Increase of mobility, m(100K)/m(300K) 4 to
  6 m T-a, a 1.5

• Increase of gm
• gm(100K)/gm(300K) (am.aI)½ (usually 2 to 3)
• With, am m(100K)/m(300K) aI
  Id(100K)/Id(300K)

• Increase of threshold voltage Vth dVth/dT
  -1mV/K

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Measurement at the lab of a TSMC 0.25mm CMOS
testchip
Measurement set up
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Measurement of TSMC CMOS at cold temperature

• DC characteristic measurement of TSMC MOS
  transistors
• Both N Mos and P Mos.
• Nmos W17.5mm L0.39mm Enclosed gate.
• Pmos W40mm L0.39mm Enclosed gate.
• Performed on transistors using a LBNL TSMC test
  chip.
• Measurement of Id-Vd and Id-Vg for T 300K,
  250K, 200K 150K, 100K and 77K. (Temp sensor
  attached to the package)
• Extraction of Vth and mobility ratio versus
  Temp.
• Comparison with simulation using the HSpice TSMC
  models.

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Threshold voltage PMOS
Slope -1mV/K
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Mobility ratio NMOS
Minimum size transistor
Spice parameter UTE -1.3
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Mobility ratio PMOS
Spice parameter UTE -0.7
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Radiation tolerance
Irradiation of deep sub micron test transistors
were performed at the lab.

• No significant change of threshold voltage was
  observed (lt50mV)
• Enclosed geometry prevents leakage at high dose
  (10 Mrad)
• Standard geometry could be used for dose lt100kRad

Standard geometry
Standard geometry
Enclosed geometry
Enclosed geometry
Dashed line Id versus Vgs before irradiation
Solid line Id versus Vgs after irradiation
(10MRad)
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Conclusion

• The RD has to provide thorough and complete
  answers on identified areas. (power, noise, cold
  temperature, radiation)
• The technology and signal processing needed to
  achieve the SNAP requirements have been selected.
• The multi slope concept has been chosen to limit
  the ADC resolution.
• A test chip design, implementing the signal
  processing building blocks has started.
• The ADC architecture study is planned.
• Deep sub micron CMOS works at low temperature
  and the behavior is predictable by Spice
  simulation.
• Good radiation tolerance of deep sub micron
  processes have been observed.