Lecture 1: Introduction to Digital Logic Design

1
Lecture 1 Introduction toDigital Logic Design

• CK Cheng
• Tuesday 4/1/02

2
We will cover four major things in this
course- Combinational Logic- Sequential
Networks- Standard Modules- System Design
3
Overall Picture of CS140
input
Memory
conditions
Mux
Control Subsystem
ALU
control
Memory
conditions
4
Two Types of Circuits
x1 . . . xn
xi
fi(x)
CLK
Combinational logic
Sequential Networks 1) Memory 2) Time Steps
(Clock)
yi fi(x1,..xn)
yit fi (x1t,xnt, s1t, snt) Sit1
gi(x1t,,xnt, s1t,.snt)
5
Part I. Combinational Logic
ab
a b
ab cd
e (abcd)
c d
cd
e

• I) Specification
• II) Implementation
• III) Different Types of Gates

6
Example Adder (counter)
5 7 1 2 Carry Sum
1 1 1 1 0 1 1 1
1
Carry bits
1 1 0 0
Carryout Sums
7
Half Adder
Truth Table
Sum ab ab Carry ab
a b carry sum 0 0 0
0 0 1 0 0 1 0
0 1 1 1 1
0
a b
carry
sum
8
Part I. Specification

1. Language
2. Truth Table
3. Boolean Expression
4. Incompletely Specified Function

9
Example Full Adder
c0
Id a b cin carry sum 0
0 0 0 0 0 1 0 0
1 0 1 2 0 1 0
0 1 3 0 1 1
1 0 4 1 0 0
0 1 5 1 0 1 1
0 6 1 1 0 1
0 7 1 1 1 1 1
a1 b1
FA
s1
c1
a2 b2
s2
c2
a3 b3
s3
s4
10
Minterm and maxterm
Id a b cin carryout 0 0
0 0 0 abc 1
0 0 1 0 abc 2
0 1 0 0 abc
3 0 1 1 1 a b c
4 1 0 0 0
abc 5 1 0 1 1 a
bc 6 1 1 0 1 a b
c 7 1 1 1 1 a b
c minterm
maxterm
11
Examples
f1(a, b, cin) abc abc abc abc
f2(a. b. cin) (abc)(abc)(abc)(abc) f
1(a, b, cin) m3 m5 m6 m7 Sm(3,5,6,7)
f2(a, b, cin) M0M1M2M4 PM(0, 1, 2,
4) abc 1 iff (a, b, c) (0, 1, 1)
abc 1 iff (a, b, c) (1, 0, 1) f1(a,b,c)
1 iff (a,b,c) (0,1,1)(1,0,1)(1,1,0)(1,1,1)
f2(abc) 0 iff (a,b,c) (0,0,0)