Combinational Logic Functions and Circuits

1
Chapter 4

• Combinational Logic Functions and Circuits

2
Functional Blocks

• Essential in understanding computer design
• since used in many places
• Code Converters
• Decoders
• Multiplexers
• Demultiplexers and Encoders

3
Multi-bit Signals and Functions

• Most non-trivial digital logic functions have
  inputs/outputs with more than 2 values
• BCD in/out need 4 bits per each digit
• Therefore a multi-bit output function is really
  composed of many single-bit functions, each a
  function of all input bits
• F (A) (F3, F2, F1, F0) where each Fi is
• Fi f(A3, A2, A1, A0)
• A multi-bit signal is known as a VECTOR

4
Vector Components and Functions

• The single-bit components of a vector are usually
  assigned the vector name with index
• Index can be ordered left-to-right or
  right-to-left
• Numbered 0 to n-1 or 1 to n
• Vector functions can be defined as unary
  constants, transfers, inversion
• Binary vector functions defined on associated
  single-bit inputs (scalers)
• Generally classified as logical, shift, arithmetic

5
Enabling

• Enable signals permit or prevent something from
  occuring (a control signal)
• State is described as either
• Active - ON or Enabled
• Passive - OFF or Disabled
• Polarity of control state can be
• Active high - schematic symbol doesnt have
  bubble
• Active low - Schematic symbol has bubble
• A single enable signal may control vector
  operations (e.g. multi-bit 3-state buffer)

6
Decoders/Demultiplexers

• A Decoder converts n-bit coded information 2n
  distinct outputs(n inputs, 2n outputs).
• Only one of the outputs, the one with index
• corresponding to the input is 1 and all others
  are zero.
• Generated outputs are actually minterms of the
  inputs.
• Example 3 to 8 decoder has 3 inputs (A0, A1, A2)
  and 8 outputs D0, D1,.D7
• If the input is 101, output is 00000100

7
Decoders
8
Decoders

• Decoder with an E(Enable) signal
• A control signal allows all outputs to be low
• when not active.Below circuit uses negative
  logic(active-0).

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Decoders
Decoder single data input, n control inputs, 2n
outputs control inputs (called select S)
represent Binary index of output to which the
input is connected data input usually called
"enable" (E or EN)
38 Decoder
24 Decoder
12 Decoder
10
Decoders
12 Decoder, Active High Enable
12 Decoder, Active Low Enable
Alternative Implementations
24 Decoder, Active High Enable
24 Decoder, Active Low Enable
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Decoders
Decoder as a Logic Building Block
A decoder is nothing more than a minterm
generator with enable
A decoder generates appropriate minterms based on
control signals, So we can implement any boolean
function using Decoders and few additional gates
Example Implement below fns. using a decoder
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Decoders
Decoder as a Logic Building Block
If active low outputs, then use NAND gates!
13
Decoders

• Hierarchical Design We want to obtain a 4 x 16
  decoder using 3x8 decoders with enable inputs.
• How many do we need?

14
1x2 dec.
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Decoders

• Alternative DesignLess gate count

A1 A2 A3
3x8 Decoder
8 outputs D0 to D7
A4
1x2 decoder
8 outputs D8 to D15
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Multiplexers/Selectors
Use of Multiplexers/Selectors
Multi-point connections
A0
A1
B0
B1
Multiple input source selection
MUX
MUX
Sa
Sb
B
A
Sum
Output
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Multiplexers/Selectors
General Concept
2n data inputs, n control inputs, 1 output used
to connect 2n points to a single point control
signal pattern form binary index of input
connected to output
Two alternative forms for a 21 Mux Truth Table
Functional form
Logical form
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Multiplexers/Selectors
n
2 -1
In general, Z ? m I
k0
k
k
n
in minterm shorthand form for a 2 1 Mux
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Multiplexers/Selectors
Gate Level Implementation of 41 Mux
I0 I1 I2 I3
Same as
2x4 decoder
A B
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Multiplexer/Selector
Large multiplexers can be implemented by cascaded
smaller ones
Control signals B and C simultaneously choose one
of I0-I3 and I4-I7 Control signal A chooses
which of the upper or lower MUX's output to gate
to Z
Alternative 81 Mux Implementation
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Multiplexers/Selectors

• Multiplexers also can be used in boolean function
  implementation
• Example Assume the inputs are A, B, C and
  F m1m3m5 and we have a 8x1 mux.
• Now use
• the select lines of the mux as A,B,C
• The input lines as 0 or 1 , 1s corresponding to
  nonzero minterms of F, that is,I1, I3, I5 in this
  case

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Multiplexers/Selectors

• Circuit is as shown below.
• This is called value fixing

I00 1 0 1 0 1 0 0
8x1 multiplexer
F
A B C
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Multiplexer/Selector
But we have an even shorter solution
2 1 multiplexer can implement any function
of n variables n-1 control variables remaining
variable is a data input to the muxA
n-1
Example
"Lookup Table"
24
Multiplexer/Selector
Generalization
Four possible configurations of the truth table
rows
n-1 Mux control variables
single Mux data variable
Can be expressed as a function of In, 0, 1
Example
G(A,B,C,D) can be implemented by an 81 MUX
K-map Choose A,B,C as control variables
Multiplexer Implementation
25
Multiplexer/Selector

• Multi-output multiplexers
• Assume you have 2 four-bit words A, B where
• A (A0,A1,A2,A3)
• Now we want to choose only one of these words,
  that is one of A , B. When S1 A should be
  selected.
• The output will have a 4 element vector

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Multiplexer/Selector

• The circuit will look like

A0 B0 A1 B1 A2 B2 A3 B3
2x1 mux
Quad multiplexer
S
2x1 mux
2x1 mux
2x1 mux
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Multiplexer/Selector

• A Multiplexer implemented with 3-state buffer
  circuits

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Multiplexer/Selector

• Also possible to implement using only 3-state
  buffers

I0 I1 I2 I3
S0
S1
Y
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Encoders and Demultiplexers

• Encoders function as reverse of decoders
• 2n inputs and n outputs
• Only one of the inputs is assumed to be 1
• Output corresponds to the index of the input
  which is 1

A00 0 0 1 0 0 0 0
D01 1 0
8x3 Encoder
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Encoders and Demultiplexers

• A Priority Encoder Input can be anything. Output
  corresponds to the input that is a first 1in
  descending order. We call it priority.
• Useful in servicing input/output devices in an
  order of priority .Some devices like a disk need
  faster service.
• A demultiplexer does the reverse of a multiplexer