Binary Counters

1
Binary Counters

• Lecture L8.3
• Section 8.2

2
Counters

• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter

3
Divide-by-8 Counter
4
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
0
1
1
1
1
Q2.D
Q2.D !Q2 Q1 Q0 Q2 !Q1
Q2 !Q0
5
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q1.D
Q1.D !Q1 Q0 Q1 !Q0
6
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q0.D
Q0.D ! Q0
7
div8cnt.abl
MODULE div8cnt TITLE 'Divide by 8
Counter' DECLARATIONS hex7seg interface(D3..D0
-gt a,b,c,d,e,f,g) d7R FUNCTIONAL_BLOCK
hex7seg " INPUT PINS " CLK PIN 12 " 1 Hz
clock (jumper) clear PIN 11 " switch 1 "
OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg'
" LED 14..16 Q Q2..Q0 "
3-bit output vector a,b,c,d,e,f,g PIN
15,18,23,21,19,14,17 ISTYPE 'com' "
Rightmost (units) 7-segment LED display
8
EQUATIONS Q.AR clear Q.C CLK Q2.D !Q2
Q1 Q0 Q2 !Q1 Q2
!Q0 Q1.D !Q1 Q0 Q1 !Q0 Q0.D
!Q0 a,b,c,d,e,f,g d7R.a,b,c,d,e,f,g d7R.
D2..D0 Q d7R.D3 0
Async clear
div8cnt.abl (contd)
Clock
9
div8cnt.abl (contd)
test_vectors(CLK -gt Q) .C. -gt 1 .C. -gt 2 .C.
-gt 3 .C. -gt 4 .C. -gt 5 .C. -gt 6 .C. -gt 7 .C.
-gt 0 .C. -gt 1 .C. -gt 2 .C. -gt 3 .C. -gt 4 END
10
div8cnt Simulation
11
Counters

• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter

12
3-Bit Down Counter
13
3-Bit Down Counter
Q1 Q0
00
01
11
10
Q2
1
0
1
1
1
1
Q2.D
Q2.D !Q2 !Q1 !Q0 Q2 Q1
Q2 Q0
14
3-Bit Down Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q1.D
Q1.D !Q1 !Q0 Q1 Q0
15
3-Bit Down Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
Q0.D
Q0.D ! Q0
16
Counters

• 3-Bit Up Counter
• 3-Bit Down Counter
• Up-Down Counter

17
Up-Down Counter
Up-Down Counter
clock
Q0 Q1 Q2
UD
UD 0 count up UD 1 count down
18
Up-Down Counter
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
UD Q2 Q1 Q0 Q2.D Q1.D Q0.D
1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1
0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0
1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1
1 1 1 1 1 0
0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1
0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1
0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0
1 1 1 0 0 0
Up-Counter
Down-Counter
19
Up-Down Counter
Q1 Q0
00
01
11
10
UD Q2
00
01
11
10
Make Karnaugh maps for Q2.D, Q1.D, and Q0.D