Registers and Counters

1
Chapter 6 Registers and Counters
2
Register - a group of binary storage cells
(flip-flops) suitable for holding binary
information. An n-bit register is a group of n
flip-flops. Counter - a register that goes
through a predetermined sequence of states.
Memory - a collection of storage cells and
circuitry to transfer data in and out of memory.
- RAM, Random Access Memory capable of both
read and write. - ROM, Read Only Memory
3
Counters
Counter - a sequential circuit which goes through
a sequence of state upon application of
input pulses. Normally, application of input
counter is the clock pulse. A binary counter
with n ff can count from 0 to 2n -1
Example - Design a 3 - bit binary counter using
T flip - flops.
0 0 0
0 0 1
1 1 1
No input. Present state is output.
0 1 0
1 1 0
0 1 1
1 0 1
1 0 0
4
Flip - Flop Inputs T A T B T C
Present State A B C
Next State A B C
0 0 0 0 0 1 0 0 1 0 0 1 0 1 0
0 1 1 0 1 0 0 1 1 0 0
1 0 1 1 1 0 0 1 1 1 1 0 0
1 0 1 0 0 1 1 0 1
1 1 0 0 1
1 1 1 0 1 1 1 0 0
1 1 1 1 0 0 0
1 1 1
B
B
0 0 1 0
0 1 1 0
0 0 1 0
A
0 1 1 0
A
TB C
C
C
TA BC
5
B
1 1 1 1
TC 1
1 1 1 1
A
C
C
A
B
T Q
T Q
T Q
1
A
B
C
CP
CP
CP
Q
Q
Q
Input
6
RegistersLatch
A4
A3
A2
A1
Q
Q
Q
Q
D
D
D
D
CP
Gate
I1
I2
I4
I3
Input
4-bit register
The data at I1 - I4 is transferred (and held)
to A1 - A4 upon receiving a clock pulse. The
data must be stable during the clock pulse.
7
Register4-Bit Register With Parallel Load
CP - Causes FF to load on negative edge of the
clock pulse. Clear Sets all FFs to 0. Load -
Enables loading. When load 0, input is cut off
S and R 0 Inputs - Inverters on R inputs
cause SR FF to become a D FF.
8
Load
S Q
A1
I1
R
I2
S Q
A3
I3
R
S Q
A4
I4
R
CP
Clear
9
RegisterWith Parallel Load using D Flip-Flops
Load - when load 0, input is cut off and all FF
outputs are fed back to their inputs. Clear -
Sets all FF to zero asynchronously
10
Load
D Q
A1
I1
D Q
A1
I2
D Q
A1
I3
D Q
A1
I4
CP
Clear
11
Registers
A register can be used as the memory device in a
sequential circuit.
Input
Output
Combinational Logic
Register
Sequential Circuit
12
Example Design a sequential circuit from this
state table
A2
0 0 0 0
A1 A1 X
A1
1 0 0 1
X
A2
0 0 0 0 0 0 0
0 1 0 1 0 0 1
0 0 1 0 0 1
1 0 0 1 1 0 0 1
0 0 1 0 1 0 1
0 1 1 0 1 1
0 1 1 1 0 0 1

0 1 0 1
A2 A2 X A2 X A2 ? X
0 1 0 1
A1
A2
X
A) State table
0 0 1 0
Y A2 X
A1
0 0 1 0
X
13
A1 A1 X
A1
A2 A2 X A2 X A2 ? X
A2
y
Y A2 X
X
Logic Diagram
Use of Register as a memory device in a
sequential circuit
14
For the previous example
ROM truth table
1 1
A1
8 x 3 ROM
2 2
A2
y
3 3
15
Shift Registers
Serial Output
Serial Input
SO
D Q
D Q
D Q
D Q
CP
Unidirectional shifting on the clock pulse,
either Right or Left. Small circle on CP input
to FF indicates a shift on the negative edge of
the CP.