Programming%20in%20Verilog

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Programming in Verilog

• CPSC 321 Computer Architecture
• Andreas Klappenecker

2
Verilog Sources

• Verilog Quickstart by James M. Lee
• 3rd edition, Kluwer, 2002
• contains Silos simulator
• gives a quick overview
• does not cover all language features
• programming style somewhat dated

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Blocks of Procedural Code

• initial
• executed once at the beginning of simulation
• initial display(Hello World)
• always
• repeatedly executed
• begin-end
• sequential execution of block statements
• delays add up
• fork-join blocks
• concurrent execution of statements

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Concurrency Example
Block 2 stmt 1 Block 1 stmt 1 Block 1 stmt
2 Block 2 stmt 2 Block 1 stmt 3 Block 2 stmt 3

• module concurrency_example
• initial begin
• 1 display(Block 1 stmt 1")
• display(Block 1 stmt 2")
• 2 display(Block 1 stmt 3")
• end
• initial begin
• display("Block 2 stmt 1")
• 2 display("Block 2 stmt 2")
• 2 display("Block 2 stmt 3")
• end
• endmodule

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Concurrency fork and join
Block 1 stmt 2 Block 2 stmt 1 Block 1 stmt
1 Block 1 stmt 3 Block 2 stmt 2 Block 2 stmt 3

• module concurrency_example
• initial fork
• 1 display(Block 1 stmt 1")
• display(Block 1 stmt 2")
• 2 display(Block 1 stmt 3")
• join
• initial fork
• display("Block 2 stmt 1")
• 2 display("Block 2 stmt 2")
• 2 display("Block 2 stmt 3")
• join
• endmodule

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Displaying Results

• a 4b0011
• display(The value of a is b, a)
• The value of a is 0011
• display(The value of a is 0b, a)
• The value of a is 11
• If you you display to print a value that is
  changing
• during this time step, then you might get the new
  or
• the old value use strobe to get the new value

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Displaying Results

• Standard displaying functions
• display, write, strobe, monitor
• Writing to a file instead of stdout
• fdisplay, fwrite, fstrobe, fmonitor
• Format specifiers
• b, 0b, d, 0d, h, 0h, c, s,

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Display Example
module f1 integer f initial begin f
fopen("myFile") fdisplay(f, "Hello, bla
bla") end endmodule
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Moore Machines
next state logic
present state register
output logic
input

• The output of a Moore machine depends
• only on the current state. Output logic and
• next state logic are sometimes merged.

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Coding Moore Machines

• The logic in the Moore machine can be described
  by two case statements
• (one case statement if logic blocks are
  merged)
• Enumerate all possible states of input and
  current state, and generate the output and next
  state
• Give states meaningful names using define or
  parameters

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Moore Machine Example

• Automatic food cooker
• Has a supply of food
• Can load food into the heater when requested
• Cooker unloads the food when cooking done

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Automated Cooker

• Outputs from the machine
• load signal that sends food into the cooker
• heat signal that turns on the heater
• unload signal that removes food from cooker
• beep signal that alerts that food is done

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Automated Cooker

• Inputs
• clock
• start start the load, cook, unload cycle
• temp_ok temperature sensor detecting when
  preheating is done
• done signal from timer when done
• quiet Should cooker beep?

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Cooker

• module cooker(
• clock, start, temp_ok, done, quiet, load, heat,
  unload, beep
• )
• input clock, start, temp_ok, done, quiet
• output load, heat, unload, beep
• reg load, heat, unload, beep
• reg 20 state, next_state

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Defining States

• define IDLE 3'b000
• define PREHEAT 3'b001
• define LOAD 3'b010
• define COOK 3'b011
• define EMPTY 3'b100

You can refer to these states as IDLE,
PREHEAT, etc.
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State Register Block

• define REG_DELAY 1
• always _at_(posedge clock)
• state lt (REG_DELAY) next_state

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Next State Logic

• always _at_(state or start or temp_ok or done)
• // whenever there is a change in input
• begin
• case (state)
• IDLE if (start) next_statePREHEAT
• PREHEAT if (temp_ok) next_state LOAD
• LOAD next_state COOK
• COOK if (done) next_stateEMPTY
• EMPTY next_state IDLE
• default next_state IDLE
• endcase
• end

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Output Logic

• always _at_(state)
• begin
• if(state LOAD) load 1 else load 0
• if(state EMPTY) unload 1 else unload 0
• if(state EMPTY quiet 0) beep 1
• else beep 0
• if(state PREHEAT
• state LOAD
• state COOK) heat 1
• else heat 0
• end