Lecture 5 Operation of a Basic Computer Architecture

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Lecture 5 - Operation of a Basic Computer
Architecture

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• Dr Richard Reilly
• Dept. of Electronic Electrical Engineering
• Room 153,
• Engineering Building

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Typical Instruction Set

• A list of instructions for our simple 16-bit CPU
• including a list of possible condition codes used
  for the program control instructions.

•  

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Typical Instruction Set
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Typical Instruction Set
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Typical Condition Codes 

• Each instruction is encoded with a 16-bit hex
  value.
• The CPU can thus uniquely decode each
  instruction.
• using an orthogonal structure the decoding is
  simplified.

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Fetch, Decode, Execute

• Processor runs a program by repeatedly fetching
  and executing instructions from main memory.
•  
• Execution of each instruction is broken down into
  two phases.
• Fetch Instruction phase
• Decode and Execute Instruction phase
• More advanced computers separate decode and
  execute into 2 phases.
• Fetch phase
• reads the instruction stored from memory at the
  location pointed to by the program counter into
  the Instruction Decode register.
• Decode and Execute phase decodes the instruction
  and executes it.

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Operation of the CPU
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Assembly Language Conventions

• Motorola Convention
• Assume all numbers are decimal
• Use to specify a HEX number, e.g. B 11
• Use to specify a constant, e.g. 12
• Use register names of Rn, e.g. R2 or ACC for
  Accumulator
• Use _at_ to specify indirect addressing
• register is used as a pointer
• Use to indicate rest of line is a comment

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Operation of the CPU
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Fetch, Decode, Execute

• Microprocessor is connected to main memory by a
  data, address and control bus.

• Need to fetch this information from memory.
• Instruction and data occupy various memory
  locations.
• Each location being identified by a unique
  address.

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Fetch, Decode, Execute

• Control bus controls the action
• Reading or Writing data to memory

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Operation of the CPU

• To start the operation of the CPU the RESET line
  is asserted (by bringing it low).
• ? This resets the PC to 0000.
•  
• After the RESET line is de-asserted (by bringing
  it high) the CPU starts operation.
• When running a program,
• processor fetches instructions by providing an
  address on the address bus and
• reading the instructions from the data bus.

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Execution of the Move Immediate

• Before running a program the PC must be
  initialised with address of first instruction.
• The first operation is to Fetch the instruction
  stored at the memory location pointed to by the
  PC,
• instruction at M0000.
•  
• Fetch Instruction
• Drive the PC onto the address bus
• Strobe the RD low
• On rising edge of the RD line, data bus is
  latched into ID register
• Increment the PC
• The PC now contains the address of the next
  instruction
• ? allows the CPU to keep track where it is in
  the program

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Operation of the CPU
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Execution of the Move Immediate

• This instruction is decoded as MOVE a constant
  (stored in the succeeding location) into register
  R0.
•     This instruction is then executed by
  fetching the data stored at M0001 into register
  R0.
• Decode and Execute Read Data into the R0
  Register
• Drive the PC onto the address bus
• Strobe the RD low
• On rising edge of RD line, data bus is latched
  into the R0 register
• Increment the PC
• Following completion of the instruction
• R0 0010
• PC 0002. Two instruction cycles required for
  this operation

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Execution of the ADD Instruction

• The execution of ADD R0 is implemented as
•  
•     Fetch
• Fetch instruction at M0002 0000
•     Decode Execute
• Add R0 to the ACC (accumulator)
•  
• The execution of other arithmetic and logical
  instructions is the same.

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Execution of the MOVE Absolute

• The next instruction is a MOVE ACC to M0200
•  Fetch
• Fetch instruction at M0003 C018
• Decode Execute
• Read data at M0004into Memory Address Register
•  Increment PC
• Execute
• Write data from ACC to memory location pointed to
  by the Memory Address Register ? M0004

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• Drive the Memory Address Register onto the
  address bus
•   Strobe the WR low
•   On the falling edge of the WR line the ACC is
  driven onto data bus
•   On the rising edge of WR line, data bus is
  latched into the memory
•   Increment the PC

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Execution of the MOVE Absolute

• The execution of the MOVE M0201 to R7 is
  implemented as
•     Fetch
• Fetch instruction at M0005 C007
•     Decode Execute
• Read data at M0006 into Memory Address Reg
•     Execute
• Write data from memory location pointed to by the
  Memory Address Reg ? M0201 into R7
•  

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Execution of MOVE Indirect

• The execution of the MOVE M_at_R7 to R1 is
  implemented as follows
•  
•    Fetch
• Fetch instruction at M0007 E001
•    Decode Execute
• Read data at MR7 into R1

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Execution of Program Control Instructions

• The execution of the JLT C is implemented as
  follows.
•   Fetch
• Fetch instruction at M0008 1204
•   Decode Execute
• If ACC lt 0 ? Read data at M0009 into PC
• If ACC ? 0 ? Do nothing

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Execution of JSR Instructions

• The execution of the JSR 100
•  
• 1. Fetch Fetch instruction at M000A 1300
• 2. Decode Execute
• Read data at M000B into temporary register
  R7100 and increment PC
• 3. Execute Push PC on to Stack 000C
• 4. Execute Write temporary register R7 000B
  to PC
•  
• Execution of NEG is the same as for arithmetic
  instructions.

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Execution of RET

• Execution of the RET is implemented as
•     Fetch
• Fetch instruction at M0101 1500
•     Decode Execute
• Pop Stack to PC 000C

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OPERATION OF A BASIC ARCHITECTURE

• A Fetch part of the instruction cycle
• ? this phase being same for all instructions.
• Following this the processor enters the
  Execution phase
• ? varies depending on type of operation
  specified in instruction.
•  
• Summary
• Programs are executed by
•     repeatedly fetching instructions from memory
  into processor
•    Execution
•  
• 3 buses are used to exchange information with the
  memory unit
•     address bus
•     data bus,
•     control bus

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Code Segment 1
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Code Segment 2