Multicycle Implementation

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Multicycle Implementation

• Assumptions
• Each STEP in the execution will take 1 clock
  cycle
• Each of these operations require 1 clock cycle
• - Memory Access ( Idealized)
• - Register File Access
• - An ALU Operation
• Any Data produced by these must be held in a
  register
• to be used in a later cycle

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MDR
IR timing requires a write control signal
4
MIPS - Lite
Consider the following instructions for
implementation INSTRUCTION OP
FUNCT R type add 0 32 subtract 0 34 AND
0 36 OR 0 37 set on less than 0 42 load
word 35 na store word 43 na branch
equal 4 na
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• Basic steps all instructions execute
• Access the Instruction from Memory
• Decode Instruction and Access the Data
• from Registers
• 3. Perform the Instruction
• 4. Write the Result

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For Multicycle Design Define S S0 , S1 , S2 ,
..., Sn Where S is the STATE of the
processor. Sk denotes that S decodes to k
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Load Word Store Word ( I type )
lw rt, imm16 (rs) or sw rt, imm16 ( rs)
op rs rt
address/ immediate
31, ... 26, 25, ... 21, 20, ... 16, 15, ...
0
lw load word M Rrs sign_ext(imm16)
Rrt sw store word Rrt M
Rrs sign_ext(imm16)
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lw rt, imm16 (rs) load word M Rrs
sign_ext(imm16) Rrt
For Op LW Next State S0 MPC
IR, PC4 PC, S1 S
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MDR
IR timing requires a write control signal
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lw rt, imm16 (rs) load word M Rrs
sign_ext(imm16) Rrt
For Op LW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A, S2
S
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MDR
IR timing requires a write control signal
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lw rt, imm16 (rs) load word M Rrs
sign_ext(imm16) Rrt
For Op LW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A, S2
S S2 A sign_ext(IR15-0) ALUOut,
S3 S
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lw rt, imm16 (rs) load word M Rrs
sign_ext(imm16) Rrt
For Op LW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A, S2
S S2 A sign_ext(IR15-0) ALUOut,
S3 S S3 M ALUOut
MDR, S4 S
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lw rt, imm16 (rs) load word M Rrs
sign_ext(imm16) Rrt
For Op LW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A, S2
S S2 A sign_ext(IR15-0) ALUOut,
S3 S S3 M ALUOut
MDR, S4 S S4 MDR R
IR20-16, S0 S
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lw rt, imm16 (rs) load word M Rrs
sign_ext(imm16) Rrt
For Op LW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A, S2
S S2 A sign_ext(IR15-0) ALUOut,
S3 S S3 M ALUOut
MDR, S4 S S4 MDR R
IR20-16, S0 S sw rt, imm16 (
rs) store word
Rrt M Rrs sign_ext(imm16)
Whats different?
16
lw rt, imm16 (rs) load word M Rrs
sign_ext(imm16) Rrt
For Op LW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B S2 S S2 A
sign_ext(IR15-0) ALUOut, S3
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S sw
rt, imm16 ( rs) store word
Rrt M Rrs sign_ext(imm16)
Whats different?
17
sw rt, imm16 ( rs) store word
Rrt M Rrs sign_ext(imm16)
For Op SW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B S2 S S2 A
sign_ext(IR15-0) ALUOut, ? S
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sw rt, imm16 ( rs) store word
Rrt M Rrs sign_ext(imm16)
For Op SW S0 MPC IR, PC4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B S2 S S2 A
sign_ext(IR15-0) ALUOut, S5 S S5 B
M ALUOut, S0 S
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MDR
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R Arithmetic Logic Instruction
op rd, rs, rt
Rrs op Rrt R rd
op rs rt rd
shamt funct
6 5 5 5
5 6
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R Arithmetic Logic Instruction
op rd, rs, rt
Rrs op Rrt R rd
Op R-type S0 MPC IR, PC 4
PC, S1 S
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R Arithmetic Logic Instruction
op rd, rs, rt
Rrs op Rrt R rd
Op R-type S0 MPC IR, PC 4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B, S6 S
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R Arithmetic Logic Instruction
op rd, rs, rt
Rrs op Rrt R rd
Op R-type S0 MPC IR, PC 4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B, S6 S S6 A op B
ALUOut, S7 S
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R Arithmetic Logic Instruction
op rd, rs, rt
Rrs op Rrt R rd
Op R-type S0 MPC IR, PC 4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B, S6 S S6 A op B
ALUOut, S7 S S7 ALUOut
RIR15-11, S0 S
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MDR
IR timing requires a write control signal
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beq rs, rt, imm16 I -type
op rs rt
address/ immediate
6 5 5
16
Zero 1 iff rs - rt 0
Zero (PC4) Zero SUM (ShLt2Sign_Ext(imm16))P
C4 PC
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beq rs, rt, imm16 I -type
Zero (PC4) Zero SUM (ShLt2Sign_Ext(imm16))P
C4 PC
Op BEQ S0 MPC IR, PC 4
PC, S1 S
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beq rs, rt, imm16 I -type
Zero (PC4) Zero SUM (ShLt2Sign_Ext(imm16))P
C4 PC
Op BEQ S0 MPC IR, PC 4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B, PC
shlt2sign_ext(IR15-0) ALUOut, S8 S
The transfers for S1 are the same for all
instructions except the next control state which
depends on the op code
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beq rs, rt, imm16 I -type
Zero (PC4) Zero SUM (ShLt2Sign_Ext(imm16))P
C4 PC
Op BEQ S0 MPC IR, PC 4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B, PC
shlt2sign_ext(IR15-0) ALUOut, S8
S S8 Zero PC Zero ALUOut PC, S0
S
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MDR
IR timing requires a write control signal
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Jump Instruction
j Label go to Label
op address
2
address
6 bits 26
bits
The complete 32 bit address is
address
00
4 bits 26 bits
2 bits
Upper 4 bits of the Program Counter, PC
jump uses word addresses
address 4 address00
This is Pseudodirect Addressing.
Note 256 MB word boundaries
32
j Label go to Label
op address
2
address
6 bits 26
bits
Op J S0 MPC IR, PC 4
PC, S1 S
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j Label go to Label
op address
2
address
6 bits 26
bits
Op J S0 MPC IR, PC 4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B, PC
shlt2sign_ext(IR15-0) ALUOut, S9 S
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j Label go to Label
op address
2
address
6 bits 26
bits
Op J S0 MPC IR, PC 4
PC, S1 S S1 RIR25-21 A,
RIR20-16 B, PC
shlt2sign_ext(IR15-0) ALUOut, S9
S S9 PC31-28 shlt2(IR25-0) PC, S0
S
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MDR
IR timing requires a write control signal
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S
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Load Word Store Word ( I type )
lw rt, imm16 (rs) or sw rt, imm16 ( rs)
op rs rt
address/ immediate
31, ... 26, 25, ... 21, 20, ... 16, 15, ...
0
lw load word M Rrs sign_ext(imm16)
Rrt sw store word Rrt M
Rrs sign_ext(imm16)
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S S5 B
M ALUOut, S0 S
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R Arithmetic Logic Instruction
op rd, rs, rt
Rrs op Rrt R rd
op rs rt rd
shamt funct
6 5 5 5
5 6
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S S5 B
M ALUOut, S0 S S6 A op B
ALUOut, S7 S
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S S5 B
M ALUOut, S0 S S6 A op B
ALUOut, S7 S S7 ALUOut
RIR15-11, S0 S
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beq rs, rt, imm16 I -type
op rs rt
address/ immediate
6 5 5
16
Zero 1 iff rs - rt 0
Zero (PC4) Zero SUM (ShLt2Sign_Ext(imm16))P
C4 PC
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S S5 B
M ALUOut, S0 S S6 A op B
ALUOut, S7 S S7 ALUOut
RIR15-11, S0 S S8 Zero PC Zero
ALUOut PC, S0 S
48
Jump Instruction
j Label go to Label
op address
2
address
6 bits 26
bits
The complete 32 bit address is
address
00
4 bits 26 bits
2 bits
Upper 4 bits of the Program Counter, PC
jump uses word addresses
address 4 address00
This is Pseudodirect Addressing.
Note 256 MB word boundaries
49
State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S S5 B
M ALUOut, S0 S S6 A op B
ALUOut, S7 S S7 ALUOut
RIR15-11, S0 S S8 Zero PC Zero
ALUOut PC, S0 S S9 PC31-28
shlt2(IR25-0) PC, S0 S
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What would Halt look like?
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9
Halt S10 S S10
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What would Halt look like?
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9
Halt S10 S S10
S10 S
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What would Start look like?
Start S0 S, boot PC
53
What if a Memory Read took 3 clock
cycles? Instead of
S0 MPC IR, PC 4 PC, S1
S
It would be S0 MPC IR S1
S S1 S2 S S2
PC 4 PC S3 S