332:437 Lecture 13 FSM Asynchronous Inputs, Clocks, and Hazards

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332437 Lecture 13FSM Asynchronous Inputs,
Clocks, and Hazards

• Asynchronous inputs
• Clock distribution
• Counters
• State reduction
• Synchronizing Sequences
• Races and Hazards
• One-Hot Design
• Summary

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Material from An Engineering Approach to Digital
Design, by William I. Fletcher, Prentice-Hall Inc.
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Asynchronous Inputs to Flip-Flops Big Problem

• Asynchronous input changes may cause flip-flop
  values to change immediately
• Differing gate propagation delays may cause
  machine to enter wrong state
• Timing requirements for positive edge-triggered
  flip-flops

tlow
1
thigh
C
0
1
tsetup
thold
D
0
D must be fixed here
D may change here
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Runt Pulse

• Logic gate inputs pulse must have minimum width
  to cause gate output to change
• Very short pulses do not cause output to change,
  but could cause a blip on gate output much later
  after a randomly-chosen Dt

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Maximum Clock Frequency

• Determined by setup and hold time on flip-flops
• Necessary relationships
• Tclock thigh tlow
• Tclock tff tcomb tsetup

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Clock Skew

• Very big problem in all electronics systems
• Caused by unequal wire length or gate delays

C1
C2
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New Clock Skew Constraints

• td thold tff (min)
• Minimum flip-flop delay
• So td tff (min) thold
• Solutions
• Never Gate the Clock! Violated all the time by
  VLSI designers to save circuit power
• Introduce matched delay l on clock line to C1
• Design clock wiring so that same wire length
  exists from clock source to all flip-flops
  (H-tree)

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Example H-Tree

• Most of VLSI circuit signal propagation delay is
  caused by the wiring
• Same distance from clock source to all Xs

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Counters

• Repeat a state after some number, N, of clock
  pulses
• Mod N remainder after dividing by N
• If counter in state n after m clock pulses, will
  be in state n after m N, m 2N, pulses
• States assigned as 0 to 2N 1
• Binary Up Counter sequence 0 to 2N 1
• Binary down counter reversed up counter
  sequence
• Decade up counter 0, 1, 2, , 10n 1, 0, 1, 2

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Ripple Counter 4-bit Binary
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Counter Timing Behavior
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Counter Categories

• ripple (asynchronous) binary
• octal
  up
• synchronous ripple carry decimal down
• parallel carry special
  up/down
• To make a counter decimal
• From count 1001 go to 0000
• Right after we enter 1010 state 000
• NOT USED because of gate races unpredictable
  counting results
• Considered to be a poor design

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Up/Down Control

• Change direction
• Use Q side to drive next clock
• Use Q signals as counter outputs
• Change negative edge to positive edge flip-flops
• Problems
• Very Slow
• Varying gate flip-flop delays can cause
  malfunctions

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Better (More Reliable) Counters

• Synchronous
• All clocks connected in parallel
• Faster
• Operation Mode Whenever all least significant
  bits are 1, next digit must change
• 0000
• 0001
• 0010 Use T flip-flops
• 0011
• 0100

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Parallel Carry Generation

• Counts only when both EnableP EnableT are 1

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Synchronous Counter with Ripple Carry

• 4 Gate delays for output carry generation as
  opposed to 1 gate delay

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Shift Registers

• Types
• Serial-in, serial-out
• Serial-in, parallel-out
• Parallel-in, parallel-out
• Bidirectional parallel-in, parallel-out
• Use a barrel shifter whenever possible
• Less hardware
• Faster

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Reduction of Finite State Machines

• Method
• Try all possible input sequences note
  differences in output sequences
• Note non-equivalent states
• Example Mealy machine

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Problems of State Partitioning

• Cannot just look for identical rows in State
  Transition Table
• Frequently, the machine cycles between three or
  more states that are actually equivalent, but the
  rows in the State Transition Table for these 3
  states do not look the same
• Therefore, just looking for identical rows causes
  you to miss equivalent states

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State Reduction by Method of Partitions

• First partition all states
• P0 (ABCDEF)
• Apply X 0 No difference in behavior
• Apply X 1 If in F, output is 1, otherwise
  output is 0
• Leads to second partition
• P1 (ABCDE) (F)
• Apply X 0 to ABCDE no output difference
• Apply X 1 to ABCDE If in ABC, stay in ABCDE
  partition, if in DE, go into another partition
  (F)
• Leads to third partition

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Method of Partitions (concluded)

• P2 (ABC) (DE) (F)
• Apply X 0 to ABC If in A, stay in ABC, if in
  BC, go to DE
• Leads to fourth partition
• P3 (A) (BC) (DE) (F)
• Apply X 0 to BC goes to DE
• Apply X 1 to BC stays in BC
• Apply X 0 to DE stays in DE
• Apply X 1 to DE goes to F
• No further partitioning possible
• Also works for Moore Machines

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Synchronizing Sequences

• Input sequence that causes a Finite State Machine
  to be in a specified state, regardless of its
  initial state at the beginning of the sequence
• Example

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Example

• Ambiguity Tree finds synchronizing sequences
• Implicitly computes differences in state behavior

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Synchronizing Sequences

• Exist for B C but not for A
• State Shortest Synchronizing Sequence
• B 1
• C 10
• Not all sequences are synchronizing sequences
  e.g., 00
• If a Synchronizing Sequence Exists for State Si,
  then it exists for all States Sj reachable from
  state Si
• Strongly Connected Finite State Machine
• All states reachable from every state

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Search of Ambiguity Tree

• Want to find SHORTEST synchronizing sequence for
  each state, so
• Search tree in a breadth-first manner
• Labels in tree are called the ambiguity
  indicate the uncertainty about which state the
  machine is in
• Once you have explored the tree for a given
  ambiguity
• If you encounter the same ambiguity again, you
  need not search it, as you will get the same
  answer you got last time you explored it

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Synchronizing Sequences

• If Synchronizing Sequence, then for a FSM to
  be strongly connected, we must have a
  synchronizing sequence for all states
• Must first reduce FSM to find the shortest
  synchronizing sequence
• Finite Memory Span FSM has finite memory span of
  length K if
• All input sequences K are synchronizing
  sequences
• Each state can be reached by a synchronizing
  sequence of length K

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Example

• Reduce
• P0 (ABCD)
• P1 (ABD) (C)
• P2 (AD) (B) (C)
• P3 (AD) (B) (C)

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Reduced Machine

• Use synchronizing sequences as state assignments
  B 00 or 10, C 01, A 11
• Use D flip-flops
• Get a shift register realization of machine

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Coded State Transition Table

• May be an inexpensive realization

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Races and Hazards

• Z-hazard a glitch on a state machine output
• Race change of more than one Flip-Flop required
  by State Transition Table
• Example going from state 10 to 01
• Non-critical race correct operation occurs no
  matter which Flip-Flop changes first
• Critical race possible to make a mistake and
  end up in the wrong state when the wrong
  Flip-Flop changes first

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Static and Dynamic Hazards

• Static Hazard Momentary transient in output
  signal that should have remained static in
  response to input change
• Exists whenever there are adjacent input
  combinations in K-Map with same output no map
  subcode covers both combinations
• Generally, 1 0 transition causes hazard
• Dynamic Hazard Multiple momentary transient in
  output signal that should have changed only once
  in response to input change
• Essential Hazard -- Operational error causing
  transition to improper state in response to input
  changes, caused by excessive delay on feedback
  variable in response to input change

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Hazard Examples

• Caused by circuit delays, which are randomly
  distributed during chip manufacturing
• Essential hazards exist only in sequential
  circuits with 2 feedbacks
• Result from a combination of both delay design
  specifications
• Can be controlled by adjusting the state
  assignment
• Requires understanding of asynchronous circuit
  design

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Static Hazards

• Theorem A static 0 (1) hazard exists if there is
  a pair of adjacent states with 0 (1) outputs and
  there is no 0 (1) set that covers both
• No static hazards in network if
• There is a 1 (0) set that covers every adjacent
  input state having an output of 1 (0)
• There are no 1 (0) sets containing exactly 1 pair
  of complemented literals
• Essential Hazard a property of the circuit
  input/output behavior
• No way to eliminate it
• There will be some combination of circuit delays
  will cause a glitch, no matter how you realize
  the circuit

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Static Hazard Example

• Static Hazard due to transition between 2
  implicants not being covered in the Karnaugh map

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Static Hazard Example

• Hazard-free SOP realization
• SOP is hazard-free, here, provided that we do not
  factor it
• Hazard in POS
• Tradeoff between simplicity of design and
  hazard-free operation

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SOP and POS Realizations

• When y 1, z 0, x 0 1, and Gate 1 is
  faster than Gate 2 in the POS realization, there
  is a Hazard in the POS realization
• SOP is hazard-free, here, provided that we do not
  factor it

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Shift Register Implementation of State Machines

• Possible if synchronizing sequence exists for all
  states and synchronizing sequence is used as
  state assignment
• Example

X
a/0
b/0
State Assignment a 1000 b 0100 c 0010 d 0001
X
X
X
d/1
c/0
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Realization
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Moebius (Johnson) Counter

• A shift register whose rightmost bit is inverted
  and fed back into its leftmost bit
• Leads to very efficient state machine realization

State Assignment a 00 b 10 c 11 d 01
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One-Hot Design

• Use 1 D Flip-Flop (FF) for each state, only 1 D
  FF set to 1 at any given time
• Advantage Look at appropriate D FF to see if the
  machine is in the corresponding state
• Grossly simplifies output decoder
• Disadvantage In a mprocessor, could lead to
  billions of FFs
• Leads to huge amounts of hardware and an
  untestable machine
• Use this method ONLY for relatively simple
  machines

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One-Hot Design of Prior Example
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State Transition Table

• State Assignment
• 1 10000
• 2 01000
• 3 00100
• 4 00010
• 5 00001

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Example (continued)

• Read out equations from Coded Table
• D1 XQ1 Z XQ5
• D2 X
• D3 XQ2
• D4 XQ3
• D5 XQ4 XQ5 X (Q4 Q5)

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Logic Gate Realization
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Summary

• Asynchronous inputs
• Clock distribution
• Counters
• State reduction
• Synchronizing Sequences
• Races and Hazards
• One-Hot Design