EE 360M Digital Systems Design Using VHDL Lecture 1

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EE 360M - Digital Systems Design Using
VHDLLecture 1

• Nur A. Touba
• University of Texas at Austin

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BASIC GATE TYPES
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FULL ADDER
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TRUTH TABLE
A
B
C
D
F
m
0 0 0 0 0 1 1 0 0 0 1
0 2 0 0 1 0 1 3 0 0 1 1
1 4 0 1 0 0 0 5 0 1 0 1
1 6 0 1 1 0 1 7 0 1 1 1
1 8 1 0 0 0 1 9 1 0 0 1
0 10 1 0 1 0 1 11 1 0 1 1
1 12 1 1 0 0 0 13 1 1 0 1
0 14 1 1 1 0 X 15 1 1 1 1 X
F S m(0,2,3,5,6,7,8,10,11) S
d(14,15)
F P M(1,4,9,12,13) S d(14,15)
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Four Variable Karnaugh Maps
F S m(0,2,3,5,6,7,8,10,11) S
d(14,15)
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Four Variable Karnaugh Maps
F P M(1,4,9,12,13) S d(14,15)
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SELECTION OF PRIME IMPLICANTS
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SIMPLIFYING 6-VARIABLE FUNCITON

• Partial truth table for 6-variable function
• G(A, B, C, D, E, F) m0 m2 m3 Em5 Em7
  Fm9 m11 m15 ( dont care terms)

ABCDEF G ABCDEF G 0000XX 1 1001X1 1 0001XX X 1010X
X X 0010XX 1 1011XX 1 0011XX 1 1101XX X 01011X 1 1
111XX 1 01111X 1
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SIMPLIFICATION USING MAP-ENTERED VARIABLES
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SIMPLIFICATION USING MAP-ENTERED VARIABLES

• G A'B' ACD E(A'D) F(AD)
• In general, Function MS0 P1MS1 P2MS2
  
• MS0 Minimal Sum when All Variables are 0
• MS1 Minimal Sum when Variable P11, All Others
  0
• MS2 Minimal Sum when Variable P21, All Others 0

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NAND/NOR GATES
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REMOVING INTERNAL INVERSION
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REMOVING INTERNAL INVERSION

• Example where Not Possible to Remove All Internal
  Inversion

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CONVERSION TO NOR GATES
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CONVERSION OF AND-OR NETWORK TO NAND GATES
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STATIC HAZARDS

• Static 1-Hazard
• Output must be 1, but momentarily goes to 0 for
  some change in inputs and some combination of
  propagation delays
• Static 0-Hazard
• If output must be 0, but momentarily goes to 1
  for some change in inputs and some combination of
  propagation delays

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EXAMPLE STATIC 1-HAZARD

• Static 1-Hazzard when A1, B, C1

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ELIMINATING STATIC-1 HAZARD
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AVOIDING STATIC HAZARDS

• Find sum-of-products expression (Ft) for output
• Where every pair of adjacent 1s covered by 1-term
  
• Two-level AND-OR network based on this Ft
• Free of 1-, 0-, and dynamic hazards
• 2. If different form of network desired,
• Manipulate Ft to desired form by simple
  factoring, DeMorgans laws, etc.
• Treat each xi and xi as independent variables
• To prevent introduction of hazards

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CLOCKED D FLIP-FLOP

• With Rising Edge Trigger

Characteristic Equation Q D
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CLOCKED JK FLIP-FLOP

• With Falling Edge Trigger

Characteristic Equation Q JQ' K'Q
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EXCITATION TABLE FOR JK FLIP-FLOP

• Q Q J K
• 0 0 0 X (No change in Q J0, K may be 1 )
• 0 1 1 X (Change to Q 1 J 1 to set or toggle)
• 1 0 X 1 (Change to Q 0 K1 to reset or
  toggle)
• 1 1 X 0 (No change in Q K0, J may be 1)

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CLOCKED T FLIP-FLOP
Q QT' Q'T Q Å T
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SR LATCH
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TRANSPARENT D LATCH
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IMPLEMENTATION OF D-LATCH

• 3rd Term (DQ) and Corresponding AND Gate
• Added to Avoid Static Hazard