EE 360M Digital Systems Design Using VHDL Lecture 5

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EE 360M - Digital Systems Design Using
VHDLLecture 5

• Nur A. Touba
• University of Texas at Austin

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SYNTHESIS FROM VHDL

• Synthesis Tools
• Infer Hardware Components From VHDL Code
• Correct Synthesis
• Requires Following Certain Conventions When
  Writing VHDL Code
• Different From Writing Computer Program
• Simulation and Synthesis Results May Not Match
• Poorly Written VHDL Code
• Timing Problems

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SIMULATION AND SYNTHESIS DIFFER
library IEEE use IEEE.numeric_bit.ALL entity Q1
is port(A, B in bit C out
bit) end Q1 architecture Q1 of Q1 is begin
process (A) begin C lt A or B after 5
ns end process end architecture
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SIMULATION AND SYNTHESIS DIFFER

• Most Synthesis Tools Will Output OR Gate
• Give Warning that B Not in Sensitivity List
• Ignore 5ns Delay
• Circuit Function Different From Simulation
• Need to Check for Warnings
• Synthesis Tool May Be Helping, or May Be
  Synthesizing Something Different Than Intended

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entity Q3 is port(A,B,F, CLK in bit
D out bit) end Q3 architecture Q3 of Q3
is signal C bit begin process(Clk)
begin if (Clk1 and Clkevent) then
C lt A and B -- statement 1
D lt C or F -- statement 2 end if
end process end Q3
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SYNTHESIS EXAMPLE

• Block Diagram from VHDL Code
• C is Internal Signal
• Is Circuit Cascade of Two Gates?

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SYNTHESIS EXAMPLE

• clkevent Implies Edge-Triggered Clock
• Flip-Flops Required for Both Statements 1 2

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VHDL CODE THAT WILL NOT SYNTHESIZE
entity nosyn is port(A,B, CLK in bit D out
bit) end no-syn architecture no-syn of no-syn
is begin process(Clk) signal C bit
begin if (Clk'1' and Clk'event) then
C lt A and B end if end
process end no-syn
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VHDL CODE THAT WILL NOT SYNTHESIZE

• Synthesis Tool
• Generates Empty Block Diagram
• Generates Warnings
• Input ltCLKgt is never used
• Input ltAgt is never used
• Input ltbgt is never used
• Output ltDgt is never assigned

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VHDL MODEL FOR MUX
F lt (not A and I0) or (A and I1)
F lt I0 when A 0 else I1
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CONDITIONAL SIGNAL ASSIGNMENT

• General Form

signal_name lt expression1 when
condition1 else expression2 when
condition2 else expressionN
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CASCADED 2-TO-1 MUXES
F lt A when E 1 else B when D
1 else C
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4-TO-1 MUX
F lt (not A and not B and I0) or (not A and B and
I1) or (A and not B and I2) or (A and B
and I3)
sel lt AB with sel select F lt I0 when
"00", I1 when "01", I2
when "10", I3 when "11"
F lt I0 when AB 00 else I1 when AB
01 else I2 when AB 10 else I3
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SELECTED SIGNAL STATEMENT

• General Form

with expression_s select signal_s lt
expression1 after delay-time when choice1
expression2 after delay-time
when choice2
expressionN after delay-time when others
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MUX MODEL IN PROCESS
case Sel is when 0 gt F lt I0 when 1 gt F
lt I1 when 2 gt F lt I2 when 3 gt F lt
I3 end case

• General Form

case expression is when choice1 gt sequential
statements1 when choice2 gt sequential
statements2 when others gt sequential
statements
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CYCLIC SHIFT REGISTER
process(CLK) begin if CLK'event and CLK '1
then Q1 lt Q3 after 5 ns Q2 lt
Q1 after 5 ns Q3 lt Q2 after 5 ns
end if end process
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REG. WITH SYNCHRONOUS CLEAR AND LOAD
process (CLK) begin if CLK'event and CLK
'1' then if CLR '1' then Q lt "0000"
elsif Ld '1' then Q lt D end
if end if end process
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LEFT SHIFT REG. WITH SYNC. CLEAR LOAD
process (CLK) begin if CLK'event and CLK
'1' then if CLR '1' then Q lt "0000"
elsif Ld '1' then Q lt D elsif Ls
'1' then Q lt Q(2 downto 0) Rin end
if end if end process
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SIMPLE SYNCHRONOUS COUNTER
signal Q unsigned(3 downto 0) ----------- proces
s (CLK) begin if CLK' event and CLK '1'
then if ClrN '0' then Q lt "0000"
elsif En '1' then Q lt Q 1 end
if end if end process
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74163 COUNTER

• Standard Part
• Available in TTL and CMOS

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74163 COUNTER
Control Signals Next State ClrN LdN PT Q
3 Q2 Q1 Q0 0 X X 0 0 0 0
(clear) 1 0 X D3 D2 D1 D0 (parallel
load) 1 1 0 Q3 Q2 Q1 Q0 (no change) 1 1 1
present state 1 (increment count)
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entity c74163 is port(LdN, ClrN, P, T, ClK
in bit D in unsigned(3 downto 0)
Cout out bit Qout out unsigned(3 downto 0)
) end c74163 architecture b74163 of c74163
is signal Q unsigned(3 downto 0) -- Q is
counter register begin Qout lt Q Cout lt
Q(3) and Q(2) and Q(1) and Q(0) and T
process (Clk) begin if
Clk'event and Clk '1' then -- change state
on rising edge if ClrN '0' then
Q lt "0000" elsif LdN '0'
then Q lt D elsif (P and T)
'1' then Q lt Q1 end if
end if end process end b74163
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8-BIT COUNTERS FROM 74163
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entity eight-bit-counter is
port(ClrN,LdN,P,T1,Clk in bit Din1,
Din2 in unsigned(3 downto 0) Count
out integer range 0 to 255 Carry2 out bit) end
eight-bit-counter architecture cascaded-counter
of eight-bit-counter is component c74163
port(LdN, ClrN, P, T, Clk in bit D in
unsigned(3 downto 0) Cout out bit
Qout out unsigned(3 downto 0) ) end component 
  signal Carry1 bit signal Qout1, Qout2
unsigned(3 downto 0) begin ct1 c74163 port
map (LdN,ClrN,P,T1,Clk,Din1,Carry1, Qout1)
ct2 c74163 port map (LdN,ClrN,P,Carry1,Clk,Din2,C
arry2, Qout2) Count lt to_integer(Qout2
Qout1) end cascaded-counter
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SYNTHESIS TIPS

• Synthesis Tools Cannot Synthesize Delays
• Most ignore after time-expression
• Some require after clauses be removed
• Initial Values Specified in Port and Signal
  Declarations
• Ignored by Synthesis Tools
• Reset signal required to set to specific value

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SYNTHESIS TIPS

• Integer Represented in Hardware as Binary Vector
• Range of Integer Determines Number of Bits
• If No Range Specified, Max. Bits Assumed
• Usually 32
• This Results in 3-Bit Counter
• This Results in 32-Bit Counter

signal count integer range 0 to 7
signal count integer
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SYNTHESIS TIPS

• VHDL Signals Retain Current Value Until Changed
• Can Result in Unwanted Latches When Synthesized
• This Statement Results in Latch to Hold B when
  X0
• This Statement Results in Combinational Logic
• For Combinational Logic
• Include else clause for every if statement

if X 1 then B lt 1 end if
if X 1 then B lt 1 else B lt 0 end if
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BLOCK DIAGRAM

• A, B, C as Inputs and F ab bc as Output

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TWO STRUCTURAL IMPLEMENTATIONS

• F ab bc Describes Functionality
• These 2 Structures Describe How Realized

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MULTIPLE LEVELS OF ABSTRACTION

• VHDL Allows Describing Hardware at Different
  Levels of Abstraction
• Behavior No hardware implied
• Dataflow (RTL) Data path plus control signals
• Structural Interconnection of components
• Synthesis Tools convert from high-level to lower
  level
• State-of-the-art Design Automation Tools
• Generate Efficient Hardware for Logic and
  Arithmetic Circuits
• Memory Structures Often Need Manual Optimizations

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MODELING SEQUENTIAL MACHINE

• BCD to Excess-3 Code Converter
• Designed in Chapter 1

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MODELING SEQUENTIAL MACHINE

• 4 Different Ways of Modeling Code Converter
• Behavioral with Separate Combinational and
  Sequental Processes
• Behavioral with Single Process
• Data Flow with Equations
• Structural

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architecture Behavioral of Code_Converter is
signal State, Nextstate integer 0 begin
process(State,X) --Combinational Network
begin case State is when 0 gt
if X'0' then Zlt'1' Nextstatelt1 end
if if X'1' then Zlt'0'
Nextstatelt2 end if when 1 gt
if X'0' then Zlt'1' Nextstatelt3 end if
if X'1' then Zlt'0' Nextstatelt4 end
if when 2 gt if X'0' then
Zlt'0' Nextstatelt4 end if if
X'1' then Zlt'1' Nextstatelt4 end if
when 3 gt if X'0' then Zlt'0'
Nextstatelt5 end if if X'1' then
Zlt'1' Nextstatelt5 end if
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when 4 gt if X'0' then
Zlt'1' Nextstatelt5 end if if X'1'
then Zlt'0' Nextstatelt6 end if when
5 gt if X'0' then Zlt'0'
Nextstatelt0 end if if X'1' then
Zlt'1' Nextstatelt0 end if when 6 gt
if X'0' then Zlt'1' Nextstatelt0 end
if when others gt null -- should not
occur end case end process
process(CLK) -- State Register begin if
CLK'1' and CLK'EVENT then -- rising edge of
clock State lt Nextstate end if
end process end Behavioral
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SIMULATION

• Can Simulate Design with Following Commands
• wave CLK X State NextState Z
• force CLK 0 0, 1 100 -repeat 200
• force X 0 0, 1 350, 0 550, 1 750, 0 950, 1 1350
• run 1600

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architecture one_process of Code_Converter is
signal State integer range 0 to 6 0 begin
process(CLK) begin if CLKevent and CLK
1 then case State is
when 0 gt if X 0 then State lt 1 else State
lt 2 end if when 1 gt if X 0'
then State lt 1 else State lt 2 end if
when 2 gt State lt 4 when 3 gt
State lt 5 when 4 gt if X 0' then
State lt 5 else State lt 6 end if
when 5 gt State lt 0 when 6 gt State
lt 0 end case end if end
process
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Z lt 1 when (State 0 and X 0) or
(State 1 and X 0) or
(State 2 and X 1) or (State 3 and X
1) or (State 4 and X
0) or (State 5 and X 1)
or State 6 else 0 end
architecture one_process
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SYNTHESIZE MEALY MACHINE

• Synthesized Implementation
• 7 Flip-Flops
• 15 2-Input AND
• 3 2-Input OR
• 1 7-input OR
• Xilinx Tool Used One-Hot
• Manual Implementation
• 3 Flip-Flops
• 4 3-Input NAND
• 3 2-Input NAND
• Used Minimal Assignment

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architecture Equations of Code_Converter is
signal Q1,Q2,Q3 bitbegin process(CLK)
begin if CLK'1' and CLKevent then --
rising edge of clock Q1ltnot Q2 after 10
ns Q2ltQ1 after 10 ns Q3lt(Q1
and Q2 and Q3) or (not X and Q1 and not Q3)
or (X and not Q1 and not Q2) after
10 ns end if end process Zlt(not X
and not Q3) or (X and Q3) after 20 nsend
Equations
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• architecture Structure of SM1_2 is signal
  A1,A2,A3,A5,A6,D3 bit'0' signal Q1,Q2,Q3
  bit'0' signal Q1N,Q2N,Q3N, XN
  bit'1'begin I1 Inverter port map
  (X,XN) G1 Nand3 port map (Q1,Q2,Q3,A1)
  G2 Nand3 port map (Q1,Q3N,XN,A2) G3
  Nand3 port map (X,Q1N,Q2N,A3) G4 Nand3
  port map (A1,A2,A3,D3) FF1 DFF port map
  (Q2N,CLK,Q1,Q1N) FF2 DFF port map
  (Q1,CLK,Q2,Q2N) FF3 DFF port map
  (D3,CLK,Q3,Q3N) G5 Nand2 port map
  (X,Q3,A5) G6 Nand2 port map (XN,Q3N,A6)
  G7 Nand2 port map (A5,A6,Z)end Structure

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USING STRUCTURAL CODE

• Using Structural Code
• Similar to In-Lining Assembly Code in Software
• Allows Designer to Fully Control Final Design
• Can Hand Optimize
• Using Behavior Code
• Often Used
• Less Design Time
• Important for Time-to-Market
• Synthesis Tools Quite Good