EE4OI4 Engineering Design

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EE4OI4Engineering Design
Introduction to VHDL
2
Introduction

• VHDL (VHSIC Hardware Description Language) is a
  language used to express complex digital systems
  concepts for documentation, simulation,
  verification and synthesis.
• VHDL is a language widely used to model and
  design digital hardware.
• The design tools make translation of design
  described in VHDL into actual working system in
  various target technologies very fast and
  reliable.
• VHDL is supported by numerous CAD tools and
  programmable logic vendors.
• VHDL was first standardized in 1987 in IEEE
  1076-1987
• An enhanced version was released in 1993

3
Outline

• Entity
• Architecture body
• Dataflow
• Behavioral
• Structural

4
Four Ways to Describe a 1-bit Comparator

• Boolean equations
• Equals lt not (a xor b)
• Concurrent statements
• Equals lt 1 when ab else 0
• Netlists
• U xnor2 port map (a,b,Equals)
• Sequential statements
• if (a b) then equals lt 1
• else equals lt 0
• end if

5
Entity Declaration

• The entity declaration describes the design I/0
  of a component,
• It is the black box representation showing
  inputs and outputs.
• Examples
• entity andgate is
• port (a,b in bit
• c out bit)
• end andgate

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Entity Declaration

• 4-bit comparator
• entity eqcomp4 is
• port (a, b in bit_vector(3 downto 0)
• equals out bit)
• end eqcomp4

eqcomp4
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Ports and Modes in Entity Declaration

• Each I/O signal in an entity declaration is
  referred to as a port. A port is a data object.
• Each port you declare must have a name, a
  direction (mode) and a data type.
• Modes Mode describes the direction of data flow,
  i.e into or out of the port or bidirectional.
• In Data flows only into the entity. Examples
  data inputs, clock, control inputs (load, reset
  etc.).
• Out Data flows out of the entity. Mode out can
  not be used for feedback. Example output
  signals seven segment display.
• Note Out does not allow internal feedback.

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Modes and Types in Entity Declaration

• Modes
• Buffer similar to mode out, except that it does
  allow for internal feedback. It does not allow
  for bidirectional dataflow.
• Inout allows data to flow into or out of the
  entity and also, allows internal feedback. Ex
  bidirectional data bus.
• Data Types
• Types provided by IEEE 1076/93 standard are most
  useful. Examples Boolean, bit, bit_vector and
  integer.
• Types provided by IEEE std_logic_1164 are
  std_ulogic and std_logic.
• Their declaration must be made visible to the
  entity by way of library and use clause.

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Data Types in Entity Declaration

• Example
• library ieee
• use ieee.std_logic_1164.all
• entity eqcomp4 is
• port (a, b in std_logic_vector(3
  downto 0)
• equals out std_logic)
• end eqcomp4
• Std_logic defines 9-value logic system
• U Uninitialized X Forcing Unknown
• 0 0 1 1
• Z High impedance L weak 0
• H weak 1 - Dont care

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VHDL design (Entity)

• Syntax for an entity declaration

entity entity_name is generic
(list-of-generics-and-their-types) port
(list-of-interface-port-names-and-their-types)
begin entity-statements end entity
entity-name

• Generic list allows additional information to
  pass into an entity
• Useful for parameterization of the design

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Architecture Bodies

• Entity is the black box with I/O description
  while architecture provides the functional
  description of that black box.
• Every architecture body is associated with an
  entity declaration.
• VHDL architectures are categorized in style as
• Behavior
• Dataflow
• Structural
• A design can use any or all of these styles.

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Example Entity and architecture body (dataflow)

• entity eqcomp4 is
• port (a, b in bit_vector(3 downto 0)
• equals out bit)
• end eqcomp4
• architecture dataflow of eqcomp4 is
• begin
• equals lt1 when (ab) else 0
• end dataflow

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Behavioral Descriptions

• Behavioral descriptions are sometimes referred to
  as high-level descriptions because of their
  resemblance to high level languages such as C and
  Fortran.
• Advantages one doesnt need to focus on the
  gate-level implementation of a design. Instead
  focus on accurately modeling its function.

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Example behavioral

• -- a four bit equality comparator
• entity eqcomp4 is
• port (a, b in std_logic_vector(3 downto 0)
• equals out std_logic)
• end eqcomp4
• architecture behavioral of eqcomp4 is
• begin
• comp process (a, b)
• begin
• if ab then
• equals lt 1
• else
• equalslt0
• end if
• end process comp
• end behavioral

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Behavioral Descriptions

• Behavioral descriptions always have a process
  statement for embodying algorithm.
• Process statement starts with an optional label
  followed by , then the reserved word process
  and a sensitivity list in the bracket.
• The process will execute when any of the signals
  named in the sensitivity list change its state.
• In our example, when a or b changes from 0 to 1
  or vice versa, the statements following the begin
  called as sequential statements will be executed.
• Although hardware is concurrent, or parallel, and
  executing simultaneously, you can model it by a
  series of sequential statements.

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Dataflow Descriptions

• Dataflow architecture specifies how data will be
  transmitted from signal to signal and input to
  output without using sequential statements.
• Behavioral architecture uses processes while
  dataflow architecture does not.
• Dataflow architectures use concurrent signal
  assignment statements while behavioral
  architectures use sequential statements.
• Concurrent statements lie outside process
  statements. The order of sequential statements in
  a process can have significant impact on the
  logic while the order of concurrent statements
  does not matter.

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Example Dataflow architecture

• library ieee
• use iee.std_logic_1164.all
• entity eqcomp4 is
• port (a, b in std_logic_vector(3 downto 0)
• equals out std_logic)
• end eqcomp4
• architecture dataflow of eqcomp4 is
• begin
• equals lt1 when (ab) else 0
• end dataflow

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Example Dataflow architecture

• library ieee
• use iee.std_logic_1164.all
• entity eqcomp4 is
• port (a, b in std_logic_vector(3 downto 0)
• equals out std_logic)
• end eqcomp4
• architecture bool of eqcomp4 is
• begin
• equals lt not(a(0) xor b(0))
• and not(a(1) xor b(1))
• and not(a(2) xor b(2))
• and not(a(3) xor b(3))
• end bool

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Identifiers

• Basic identifiers are made up of alphabetic,
  numeric and/or underscore characters.
• The first character must be a letter.
• The last character can not be an underscore.
• Two underscores in succession are not allowed.
• VHDL reserved words such as entity, is,
  architecture should not be used as identifiers.
• Upper and lower case letters are equivalent when
  used in identifiers. The following are
  equivalent
• Clk, clk, CLK, clK

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Comparison of Logic Technologies

• Traditional IC chips such as MSI TTL perform a
  fixed operation defined by the device
  manufactures. The user must connect the chips to
  build a circuit.
• Application Specific Integrated Circuits (ASIC),
  Complex Programmable Logic Devices (CPLD) and
  Field Programmable Gate Array (FPGA) are ICs
  whose internal function is defined by the user.
• For CPLD or FPGA, user programming is required to
  perform the desired operation while ASIC requires
  a customized manufacturing step for the user
  defined operation.

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Identify the legal identifiers

• 1. _tx_clk?
• 1. No. must start with a letter.

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Concurrent statements

• Assignment statements, selected assignment
  statements and conditional assignment statements
  are called concurrent statements because the
  order in which they appear is not important.
• Concurrent statements are executed in parallel.
• Each concurrent statement is different hardware
  element operating in parallel.

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Combinational Logic

• Combinational logic can be implemented with
  concurrent and sequential statements.
• Concurrent statements are used in dataflow and
  structural descriptions.
• Sequential statements are used in behavioral
  descriptions.

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Using Concurrent Statements

• Boolean equations
• Selective signal assignment (with-select-when)
• Conditional signal-assignment (when-else)

MUX
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Boolean Equations Implementation of MUX

• entity mux is port(
• a,b,c,d in std_logic_vector(3 downto 0)
• s in std_logic_vector(1 downto
  0)
• x out std_logic_vector(3
  downto 0)
• end mux
• architecture bool of mux is
• begin
• x(3) lt (a(3)and not s(1)and not s(0)) or
  (d(3)and s(1)and s(0))
• or (b(3)and not s(1)and s(0))or
  (c(3)and s(1)and not s(0))
• x(2) lt .
• end bool

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with-select-when

• This provides selective signal assignment, which
  means that a signal is assigned a value based on
  the value of selection signal.
• with selection_signal select
• Signal_name lt value_1 when value_a_of
  selection_signal,
• value_2 when
  value_b_of selection_signal,
• value_3 when
  value_c_of selection_signal,
• value_n when
  last_value_of selection_signal

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with select when implementation of MUX

• entity mux is port(
• a,b,c,d in std_logic_vector(3 downto 0)
• s in std_logic_vector(1 downto
  0)
• x out std_logic_vector(3
  downto 0)
• end mux
• architecture with_select_when of mux is
• begin
• with s select
• x lt a when 00,
• b when 01,
• c when 10,
• d when others
• end with_select_when

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when_else

• The signal is assigned a value based on a
  condition.
• Signal_name lt value_1 when condition1 else
• value_2 when
  condition2 else
• value_3 when
  condition3 else
• value_n.

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when-else implementation of MUX

• entity mux is port(
• a,b,c,d in std_logic_vector(3 downto 0)
• s in std_logic_vector(1 downto
  0)
• x out std_logic_vector(3
  downto 0)
• end mux
• architecture when_else of mux is
• begin
• x lt a when (s00) else
• b when (s01) else
• c when (s10) else
• d
• end when_else

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Relational Operators

• Relational operators are used for testing
  equality, inequality, and ordering.
• The equality () and inequality (/) operators
  are defined for all types.
• The magnitude operators (lt,gt,lt,gt) are defined
  for scalar types or an array with a discrete
  range.
• The result of any relational operator is Boolean.
• The types of operands in relational operators
  must match. Suppose a is a std_logic_vector and
  3 is an integer. The statement
• if a 3 then
• would produce an error.

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Overloaded Operators

• Behavioral descriptions always have a process
  statement for embodying algorithm.
• Process statement starts with an optional label
  followed by , then the reserved word process
  and a sensitivity list in the bracket.
• The process will execute when any of the signals
  named in the sensitivity list change its state.
• In our example, when a or b changes from 0 to 1
  or vice versa, the statements following the begin
  will be executed sequentially until the end
  statement.

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Behavioral Descriptions

• Behavioral descriptions always have a process
  statement for embodying algorithm.
• Process statement starts with an optional label
  followed by , then the reserved word process
  and a sensitivity list in the bracket.
• The process will execute when any of the signals
  named in the sensitivity list change its state.
• In our example, when a or b changes from 0 to 1
  or vice versa, the statements following the begin
  will be executed sequentially until the end
  statement.

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Introduction

• VHDL consists of several parts organized as
  follows
• Actual VHDL language specified by IEEE
• Some additional data type declarations in the
  standard package called IEEE standard 1164
• A WORK library reserved for users designs
• Vendor packages with vendor libraries
• User packages and libraries

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VHDL design

• A VHDL design consists of several design units
  (building blocks)
• The designer defines the basic building blocks in
  the following sections
• Library
• Package
• Entity
• Architecture
• Configuration

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VHDL Design
Library
Entity
Package
Package Body
Architecture1
Architecture2
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VHDL design (Library)

• Results of a VHDL compilation are stored in a
  library for subsequent simulation or use in other
  designs.
• A library can contain
• Package (shared declarations)
• Entity (shared designs)
• An architecture (shared design implementation)
• Two built-in libraries are WORK and STD
• User can create other libraries
• VHDL source design units are complied into WORK
  library

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VHDL design (Library)

• To use a library it should be declared
• Exp library ieee
• If WORK library is used it does not need to be
  declared
• Complied units in a library can be accessed via a
  use statement
• Syntax
• use library_name.package_name.item_name
• use library_name.item_name
• Exp use ieee.std_logic_1164.all

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VHDL design (Package)

• Next level of hierarchy within a library is a
  package.
• A package collects a group of related declaration
  together
• A package is used for
• Function and procedure declaration
• Type and subtype declaration
• Constant declaration
• File declaration
• Package is created to store common data types,
  constants and complied designs that will be used
  in more than one design (reusability)

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VHDL design (Package)

• All vendors provide a package named STANDARD in a
  predefined library named STD. This package
  defines useful data types
• There is also a text I/O package called TEXTIO in
  STD.
• A use clause allows access to a package in a
  library
• No use clause is required for the package
  STANDARD (it is default)

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Entity Architecture

• A VHDL design is a paring of an entity
  declaration and an architecture body.
• Entity declaration describes the design I/O and
  my include parameters used to customize an entity
• Architecture body describes the function of a
  design
• Each I/O signal in an entity declaration is
  referred to as a port
• A port is a data object
• Like other data objects it can be assigned values
  and used in expressions

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Entity Architecture

• Each port you declare must have a name, a
  direction (mode) and a data type.
• Mode describes the direction in which data is
  transferred through a port
• Mode can be one of 4 values in, out, inout, or
  buffer
• In data flows only into the entity. The driver
  of the port is external (e.g., clock input)
• Out data flows only from its source (inside the
  entity) to the port
• Note out does not allow feedback

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Entity Architecture

• Buffer for internal feedback (to use a port also
  as a driver within the architecture)
• Buffer is used for ports that must be readable
  inside the entity, such as the counter outputs
  (the present state of a counter must be used to
  determine its next stage
• Inout allows data to flow into or out of the
  entity. It also allows for internal feedback
• Mode inout can replace any of the other modes

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Entity Architecture

• In addition to specifying modes for ports, you
  must declare data types for ports
• The most important data types in VHDL are
  Boolean, bit, bit_vector, and integer
• The most useful types provided by the IEEE
  std_logic_1164 package is std_logic and array of
  this type.
• For simulation and synthesis software to process
  these types, their declaration must be made
  visible to the entity by way of library and use
  clauses

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VHDL design (Architecture)

• An architecture specifies the behavior,
  interconnections and components of an entity.
• Architecture defines the function of an entity
• It specifies the relationship between inputs and
  outputs.
• VHDL architectures are categorized in style as
• Behavior
• Dataflow
• Structural
• A design can use any or all of these styles.

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VHDL design (Architecture)

• Behavior the behavior of the entity is expressed
  using sequentially executed procedural code (very
  similar to programming languages like C)
• Uses process statement and sequential statements
  (the ordering of statements inside process is
  important)
• Dataflow specifies the functionality of the
  entity (the flow of information) without
  explicitly specifying its structure
• No use of process or sequential statements
• Structural an entity is modeled as a set of
  components connected by signals
• Components are instantiated and connected
  together

46

• library ieee
• use iee.std_logic_1164.all
• entity eqcomp4 is port (a, b in
  std_logic_vector(3 downto 0)
• equals out std_logic)
• end eqcomp4
• use work.gatespkg.all
• architecture struct of eqcomp4 is
• signal x std_logic_vector(0 to 3)
• begin
• u0 xnor2 port map (a(0),b(0),x(0))
• u1 xnor2 port map (a(1),b(1),x(1))
• u2 xnor2 port map (a(2),b(2),x(2))
• u3 xnor2 port map (a(3),b(3),x(3))
• u4 and4 port map(x(0), x(10, x(2), x(3),
  equals)
• end struct

47
x
1
x
2
f
x
3
A simple logic function and corresponding VHDL
code
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VHDL

• The first step is to define the input, output
  signals.
• This is done using a construction called entity.
• The circuits functionality must be specified with
  a VHDL construction called an architecture.
• lt is the signal assignment operator in VHDL
• VHDL does not assume any precedence of operation
  and therefore parentheses are necessary in VHDL
  expressions.
• Whenever there is an event on x1, x2, x3, the
  expression on the right side is evaluated and the
  value appears on f.

49
x
1
x
3
f
x
2
g
x
4
Logic circuit for four-input function
50
Figure 2.30 VHDL code for a four-input function
51
Example

• The signal assignments in the previous example
  are concurrent statements.
• Concurrent statements are order independent.

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VHDL

• Another data type defined in VHDL STD_LOGIC
• STD_LOGIC can have a number of legal values 0,
  1, z, -
• To use STD_LOGIC type the VHDL code must have
  these two lines
• LIBRARY ieee
• USE ieee.std_logic_1164.all
• The first line declares that the code will use
  ieee library

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Figure5.4 Full-adder
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LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY fulladd IS PORT ( Cin, x, y IN
STD_LOGIC s, Cout OUT STD_LOGIC ) END
fulladd ARCHITECTURE LogicFunc OF fulladd
IS BEGIN s lt x XOR y XOR Cin Cout lt (x AND
y) OR (Cin AND x) OR (Cin AND y) END LogicFunc
Figure 5.23 VHDL code for the full-adder
55
VHDL

• Now if we want to create a 4-bit adder we can use
  the 1-bit adder already designed as a
  sub-circuit.
• This is an important feature of VHDL which makes
  the reuse of entities possible.
• Two ways to do this a command named COMPONENT or
  using PACKAGE.
• Every time the entity is used it is instantiated
• Every instantiation has a name.

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LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY adder4 IS PORT ( Cin IN STD_LOGIC
x3, x2, x1, x0 IN STD_LOGIC y3, y2,
y1, y0 IN STD_LOGIC s3, s2, s1, s0
OUT STD_LOGIC Cout OUT STD_LOGIC )
END adder4 ARCHITECTURE Structure OF adder4
IS SIGNAL c1, c2, c3 STD_LOGIC COMPONENT
fulladd PORT ( Cin, x, y IN STD_LOGIC
s, Cout OUT STD_LOGIC ) END
COMPONENT BEGIN stage0 fulladd PORT MAP (
Cin, x0, y0, s0, c1 ) stage1 fulladd PORT MAP
( c1, x1, y1, s1, c2 ) stage2 fulladd PORT
MAP ( c2, x2, y2, s2, c3 ) stage3 fulladd
PORT MAP ( Cin gt c3, Cout gt Cout, x gt x3, y
gt y3, s gt s3 ) END Structure
Figure 5.24 VHDL code for a four-bit adder
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Data objects

• Data objects hold values of specific types
• Data objects belong to one of four classes
  constant, signals, variables, or files
• Constant holds a value that cannot be changed
  within the design
• Exp width of a register
• constant width integer 8
• Constant can be declared in package, entity,
  architecture, or process
• Defined in a package can be referenced by any
  entity or architecture for which the package is
  used

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Data objects

• Defined in an entity declaration is visible only
  within the entity
• Defined in an architecture is visible only to the
  architecture
• Defined in a process declarative region is
  visible only to that process
• Signals represent wires, and therefore
  interconnect components
• Ports are signals
• signal count bit_vector(3 downto 0)

59
Data objects

• Variables used only in processes, functions and
  procedures
• They are usually used for computational purposes
  in high level modeling (e.g., index, temporary
  storage of data)
• The variable assignment and initialization symbol
  indicates immediate assignment
• Files contain values of a specific type

60
Data types

• Besides predefined types (e.g., BIT, STD_LOGIC)
  user can define their own types in VHDL.
• The command for this purpose is type
• Example
• type DIGIT is (0,1,2,3,4,5,6,7,8
  ,9)
• A subtype is a type with a constraint
• Example
• subtype MIDDLE is DIGIT range 3 to 7

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Data types

• Arrays of predefined or user defined types can be
  introduced.
• Example
• type ADDRESS_WORD is array (0 to 63) of BIT
• type DATA_WORD is array (7 downto 0) of STD_LOGIC
• In the first example ADDRESS_WORD(0) is the most
  significant bit and in the second one
  DATA_WORD(7) is the most significant bit.
• There is a predefined array type in ieee library
  STD_LOGIC_VECTOR
• It can be used for presentation of multibit
  signals.

62
Data types

• An array object can be assigned to another array
  object of the same type.
• Assignment can be made to an entire array, or to
  an element or to a slice.
• Example
• SIGNAL X STD_LOGIC_VECTOR(3 to 0)
• X lt1100
• X(3) lt0
• X(0 to 2) lt101

63
Data types

• Now that we have multibit numbers we are able to
  represents numbers.
• Are we able to perform arithmetic operations on
  the numbers in VHDL?
• Another package named std_logic_arith defines
  types for this
• Two predefined types in this package SIGNED and
  UNSINGED
• SIGNED and UNSIGNED are similar to
  STD_LOGIC_VECTOR
• Unsigned represents unsigned integer data in the
  form of an array of std_logic
• Singed represents signed integer data in twos
  complement form

64
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_arith.all ENTITY adder16
IS PORT ( Cin IN STD_LOGIC X, Y IN
SIGNED(15 DOWNTO 0) S OUT SIGNED(15
DOWNTO 0) Cout, Overflow OUT STD_LOGIC )
END adder16 ARCHITECTURE Behavior OF adder16
IS SIGNAL Sum SIGNED(16 DOWNTO 0)
BEGIN Sum lt ('0' X) Y Cin S lt
Sum(15 DOWNTO 0) Cout lt Sum(16) Overflow
lt Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) END
Behavior
Figure 5.30 Use of the arithmetic package
65
4-bit up-down counter

• library ieee
• use ieee.std_logic_1164.all
• use ieee.std_logic_unsigned.all
• entity counter is port (clk, load, up, down in
  std_logic data in std_logic_vector(3 downto 0)
  count out std_logic_vector(3 downto 0))
• end counter
• architecture count4 of counter is
• signal cnt std_logic_vector(3 downto 0)
• begin
• process (clr, clk)
• begin
• if clr1 then cntlt0000
• elsif clkevent and clk1 then
• if load1 then cntltdata
• elsif up1 then

66
4-bit up-down counter

• if cnt1111 then cnt lt0000
• else cntltcnt1
• endif
• elsif down1 then
• if cnt0000then cntlt1111
• else cntltcnt-1
• end if
• else cntltcnt
• end if
• end if
• countltcnt
• end process
• end count4

67
Selected signal assignment

• Selected signal assignment is used to assign one
  of multiple values to a signal, based on some
  criteria.
• The WITH WHEN structure can be used for this
  purpose.

68
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY mux2to1 IS PORT ( w0, w1, s IN
STD_LOGIC f OUT STD_LOGIC ) END
mux2to1 ARCHITECTURE Behavior OF mux2to1
IS BEGIN WITH s SELECT f lt w0 WHEN
'0', w1 WHEN OTHERS END Behavior
Figure 6.27 VHDL code for a 2-to-1 multiplexer
69
Conditional signal assignment

• Conditional signal assignment is used to assign
  one of multiple values to a signal, based on some
  criteria.
• The WHEN ELSE structure can be used for this
  purpose.

70
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all ENTITY compare
IS PORT ( A, B IN STD_LOGIC_VECTOR(3 DOWNTO
0) AeqB, AgtB, AltB OUT STD_LOGIC ) END
compare ARCHITECTURE Behavior OF compare
IS BEGIN AeqB lt '1' WHEN A B ELSE '0'
AgtB lt '1' WHEN A gt B ELSE '0' AltB lt '1'
WHEN A lt B ELSE '0' END Behavior
Figure 6.34 VHDL code for a four-bit comparator
71
VHDL

• Syntax of architecture body
• architecture architecture_name of entity_name is
• architecture_item_declaration
• begin
• concurrent_statements these are
• concurrent_assignment
• process_statement
• block_statement
• concurrent_procedure_call_statement
• component_instantiation_statement
• generate_statement
• end

72
Sequential statements

• Sequential statements ordering of statements may
  affect the meaning of the code
• Sequential statements should be placed inside
  process statement.
• Process itself is a concurrent statement

73
Process

• process_label process (sensitivity_list)
  is
• process_item_declaration
• begin
• sequential_statements these are
• variable_assignment
• signal_assignment
• wait_statement
• if_statement
• case_statement
• loop_statement
• null_statement
• exit_statement
• next_statement
• report_statement
• return_statement
• end process process_label

74
Process

• Sensitivity list signals to which the process is
  sensitive
• Each time an event occurs on any of the signals
  in sensitivity list, the sequential statements
  within the process are executed in the order they
  appear

75
If statement

• An if statement selects a sequence of statements
  for execution based on the value of a condition
• Syntax
• If boolean_expression then
• sequential_statements
• elsif boolean_expression then
• sequential_statements
• else
• sequential_statements
• end if

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LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY mux2to1 IS PORT ( w0, w1, s IN
STD_LOGIC f OUT STD_LOGIC ) END
mux2to1 ARCHITECTURE Behavior OF mux2to1
IS BEGIN PROCESS ( w0, w1, s ) BEGIN IF s
'0' THEN f lt w0 ELSE f lt w1 END
IF END PROCESS END Behavior
A 2-to-1 multiplexer specified using an
if-then-else statement
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Case

• Syntax
• case expression is
• when choices gt sequential_statements
• when choices gt sequential_statements
• ..
• when others gt sequential_statements
• end case

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LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY seg7 IS PORT ( bcd IN
STD_LOGIC_VECTOR(3 DOWNTO 0) leds OUT
STD_LOGIC_VECTOR(1 TO 7) ) END seg7
ARCHITECTURE Behavior OF seg7
IS BEGIN PROCESS ( bcd ) BEGIN CASE bcd IS
-- abcdefg WHEN "0000" gt leds lt
"1111110" WHEN "0001" gt leds lt
"0110000" WHEN "0010" gt leds lt
"1101101" WHEN "0011" gt leds lt
"1111001" WHEN "0100" gt leds lt
"0110011" WHEN "0101" gt leds lt
"1011011" WHEN "0110" gt leds lt
"1011111" WHEN "0111" gt leds lt
"1110000" WHEN "1000" gt leds lt
"1111111" WHEN "1001" gt leds lt
"1110011" WHEN OTHERS gt leds lt
"-------" END CASE END PROCESS END
Behavior
a
b
f
g
c
e
d
Figure 6.47 A BCD-to-7-segment decoder
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Wait

• When a process has a sensitivity list it is
  always suspended after executing the last
  statement in the process
• Wait is an alternative way of suspending a
  process
• Syntax
• wait on sensitivity_list
• wait until boolean_expression
• wait for time_expression

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LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY flipflop IS PORT ( D, Clock
IN STD_LOGIC Q OUT STD_LOGIC) END
flipflop ARCHITECTURE Behavior OF flipflop IS
BEGIN PROCESS ( Clock ) BEGIN IF
Clock'EVENT AND Clock '1' THEN Q lt D
END IF END PROCESS END Behavior
Figure 7.38 Code for a D flip-flop
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LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY flipflop IS PORT ( D, Clock IN
STD_LOGIC Q OUT STD_LOGIC ) END
flipflop ARCHITECTURE Behavior OF flipflop IS
BEGIN PROCESS BEGIN WAIT UNTIL
Clock'EVENT AND Clock '1' Q lt D END
PROCESS END Behavior
Figure 7.39 Code for a D flip-flop using WAIT
UNTIL
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Event

• EVENT is a predefined attribute of a signal and
  is true if an event (a change in value) occurred
  on that signal at the time the value of the
  attribute is determined.

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Loop statement

• Loop iterates through a set of sequential
  statements
• Syntax
• loop_label iteration_scheme loop
• sequential_statements
• end loop loop_label
• 3 types of iteration_schemes
• for identifier in range
• while boolean_expression
• No iteration scheme is specified and some other
  action causes the loop to be terminated (use of
  exit, next or return)

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LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY shiftn IS GENERIC ( N INTEGER 8 )
PORT ( R IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) Clock IN STD_LOGIC L, w IN
STD_LOGIC Q BUFFER STD_LOGIC_VECTOR(N-1
DOWNTO 0) ) END shiftn ARCHITECTURE Behavior
OF shiftn IS BEGIN PROCESS BEGIN WAIT UNTIL
Clock'EVENT AND Clock '1' IF L '1'
THEN Q lt R ELSE Genbits FOR i IN 0 TO
N-2 LOOP Q(i) lt Q(i1) END LOOP
Q(N-1) lt w END IF END PROCESS END
Behavior
Code for an n-bit left-to-right shift register
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Exit

• Exit causes execution to jump out of the
  innermost loop or the loop whose label is
  specified.
• Syntax
• exit loop_lablewhen condition
• Example
• L3 loop
• JJ21
• sumsum10
• if sumgt100 then
• exit L3
• end if
• end loop L3

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Next

• Next a sequential statement that can be used
  only inside a loop
• It results in skipping the remaining statements
  in the current iteration. Execution resumes with
  the first statement in the next iteration of the
  loop
• Syntax
• next loop_labelwhen condition
• Example
• for j in 10 downto 5 loop
• if sumlttotal_sum then
• sumsum2
• elsif sumtotal_sum then
• next
• else
• null
• end if
• kk1
• end loop

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Null

• No action takes place
• Syntax
• null

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Data types

• Every object in VHDL can hold a value that
  belongs to a set of values
• This set is specified by a type declaration
• A type is a name that has associated with it a
  set of values and a set of operation
• All possible types can be categorized into 4
  groups
• Scalar type values belonging to these types
  appear in sequential order
• Composite types composed of elements of single
  type (array) or different type (record)
• Access type
• File type

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Scalar types

• The values belonging to these types are ordered
• Relational operators (gt,lt) can be used on the
  values of these types

Scalar types
Enumeration
Integer
Physical
Floating point
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Enumeration types

• Exp type MVL is (U,0,1,Z)
• The order in which values appear in an
  enumeration type declaration defines their
  ordering
• Using a relational operator, a value is always
  less than a value that appears to its right in
  the order
• Values of an enumeration type also have a
  position number associated with them
• The position number of the leftmost element is 0.
• The predefined enumeration types are Character,
  Bit, Boolean, Severity_level.
• Std_logic is an enumerated type defined in
  std_logic_1164

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Integer types

• Integer type a type whose set of values fall
  within a specified integer range
• Exp
• Type index is integer range 0 to 15
• Type word_length is range 31 downto 0
• The position of each value of an integer type is
  the value itself
• Values belonging to an integer type are called
  integer literals
• The underscore character can be used freely in
  writing integer literals and has no impact on the
  value of a literal
• Exp 98_71_28 is the same as 987128

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Physical types

• Physical types values that represent measurement
  of some physical quantity (e.g., time, length,
  .)
• Exp
• type current is range 0 to 1E9
• units
• nA
• uA 1000 nA
• mA 1000 uA
• Amp 1000mA
• end units
• a5.6 nA

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Floating point type

• Floating point type a set of values in a given
  range of real numbers
• Exp
• type ttl_voltage is range 5.5 to 1.4

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Composite types
Composite types
Array type All values belong to a single type
Record type a collection of values that may
belong to different types
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Array type

• Elements having the same type
• Exp
• type address_word is array (0 to 63) of bit
• type data_word is array (7 downto 0) of
  std_logic
• type ROM is array (0 to 125) of data_word
• type decode_matrix is array (positive range 15
  downto 1, natural range 3 downto 0) of std_logic
• Positive and natural are predefined subtypes of
  integer
• subtype natural is integer range 0 to
  integerhigh
• subtype positive is integer range 1 to
  integerhigh

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Array type

• VHDL allows the number of elements in the array
  type not to be specified in the type declaration
  (unconstrained arrays)
• An object declaration for an object of that type
  declares the number of elements of the array
• Exp
• type stack_type is array (integer range ltgt) of
  address_word
• variable fast_stk stack_type(-127 to 127)

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Array type

• Two predefined 1-D unconstrained array types in
  VHDL string and bit_vector
• String array of characters
• Bit_vector array of bits
• Exp
• variable message string(1 to 17) Hello, VHDL
  world
• signal rx_bus bit_vector(0 to 5)
• Predefined 1-D unconstrained array type in
  std_logic_1164 std_logic_vector

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Record type

• An object of record type is composed of elements
  of same or different types
• Exp
• type pin_type is integer range 0 to 10
• type module is
• record
• size integer range 20 to 30
• critical_dly time
• no_inputs pin_type
• no_outputs pin_type
• end record
• variable nand_comp module
• nand_comp (50, 20 ns, 3, 2)

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Type conversion

• to_stdlogicvector(bit_vector) converts a bit
  vector to a standard logic vector
• example to_stdlogicvector(XFFFF)
• conv_std_logic_vector(integer, bits) converts an
  integer to a standard logic vector
• example conv_std_logic_vector(7,4) generates
  0111
• conv_integer(std_logic_vector) converts a
  standard logic vector to an integer
• example conv_integer(0111) produces 7

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lpm modules
Name Description
Gates lpm_and lpm_inv lpm_bustri lpm_mux lpm_clshift lpm_or lpm_constant lpm_xor lpm_decode mux busmux Multi-bit and gate Multi-bit inverter Multi-bit three state buffer Multi-input multi-bit multiplexer Combinatorial logic shifter and barrel shifter Multi-bit or gate Constant generator Multi-bit xor gate Decoder Single input multi-bit multiplexer Two-input multi-bit multiplexer
Arithmetic Components divide lpm_compare lpm_abs lpm_counter lpm_add_sub lpm_divide lpm_mult Parameterized Divider Two-input multi-bit comparator Absolute value Multi-bit counter with various control options Multi-bit adder subtractor Parameterized Divider Multi-bit multiplier
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lpm modules
Name Description
Gates altdpram lpm_latch csfifo lpm_shiftreg dcfifo lpm_ram_dp scfifo lpm_ram_dq csdpram lpm_ram_io lpm_ff lpm_rom lpm_fifo lpm_dff lpm_fifo_dc lpm_tff Parameterized Dual-Port RAM Parameterized Latch Cycle shared first-in first-out buffer Parameterized Shift Register Parameterized Dual-Clock FIFO Parameterized Dual-Port RAM Parameterized Single-Clock FIFO Synchronous or Asynchronous RAM with a separate I/O ports Cycle shared dual port RAM Synchronous or Asynchronous RAM with a single I/O port Parameterized flip flop Synchronous or Asynchronous ROM Parameterized Single-Clock FIFO Parameterized D-Type flip flop and Shift Register Parameterized Dual-Clock FIFO Parameterized T-Type flip flop
Other functions clklock pll ntsc Parameterized Phase-Locked Loop Rising- and Falling-Edge Detector NTSC Video Control Signal Generator
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Operators
Operators
Logic
Miscellaneous
Relational
Shift
Adding
Multiplying

• Logic operators and, or, nand, nor, xor, xnor,
  not
• Logic operators are defined on types bit ,
  std_logic and Boolean or their 1-D arrays

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Operators

• Relational operators , /, lt, lt, gt, gt
• and / are defined on any type
• The remaining relational operators are defined on
  any scalar type
• Shift operators sll, srl, sla, sra, rol, ror
• Each takes an array of bit or Boolean as the left
  operand and an integer value as the right operand
  and performs the specified operation
• Sll (shift left logically) fills the vacated bit
  with left_operand_typeLEFT
• Sla (shift left arithmetic) fills the vacated
  bit with the rightmost bit of the left operand
• Rol rotate left
• Exp
• 1001010 sll 2 is 0101000
• 1001010 sla 2 is 0101000
• 1001010 rol 2 is 0101010
• xlta sll 2, if a is an 8 bit std_logic, x(7
  downto2) is a(5 downto 0) and x(1) and x(0) are
  zero

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Operators

• Adding operators, , -,
• The operands for and must be of the same
  numeric type
• The operands for (concatenation) can be either
  a 1-D array or an element type
• Exp cat the result cat
• Multiplying operators, /, mod, rem
• and / are defined for both operands being
  integers or float
• is also defined when one operand is of physical
  type and the second of integer or real type
• / division of a physical type by an integer or
  float is allowed
• / of two object of the same physical type is
  also allowed

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Operators

• abs is defined for any numeric type
• is defined for left operand to be integer or
  float and right operand to be of integer type
  only

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