Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip

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Legacy SystemC Co-Simulation of Multi-Processor
Systems-on-Chip

• L. Benini, D. Bertozzi, D. Bruni, N. Drago, F.
  Fummi, M. Poncino
• Proceedings of IEEE International Conference on
  Computer Design (ICCD), Page 494-499, 16-18 Sept.
  2002

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Abstract

• We present a co-simulation environment for
  multiprocessor architectures, that is based on
  SystemC and allows a transparent integration of
  instruction set simulators (ISSs) within the
  SystemC simulation framework. The integration is
  based on the well-known concept of bus wrapper,
  that realizes the interface between the ISS and
  the simulator. The proposed solution uses an
  ISS-wrapper interface based on the standard gdb
  remote debugging interface, and implements two
  alternative schemes that differ in the amount of
  communication they require. The two approaches
  provide different degrees of tradeoff between
  simulation granularity and speed, and show
  significant speedup with respect to a
  micro-architectural, full SystemC simulation of
  the system description.

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Outline

• Whats the Problem
• Related Works
• Proposed Methods (alternative)
• Experimental Results
• Conclusions

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Whats the Problem

• Conventional co-simulation scheme waste much
  simulation time
• Need to find method to speedup
• Disadvantages of conventional co-simulation
• Mixed language (need time to learning differ
  ones)
• Slow simulation time Co-simulation with HW RTL
  code

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Region of Problem
CAD Tool
Simulation
Synthesis
Layout
High level
Low level
Co-simulation
Mixed Language
Single Language
With ISS
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Related Works

• Conventional co-simulation
• Without Instruction set simulator (ISS)
• With ISS

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Co-simulation Operating

• Environment assumption
• Cross-compiler
• Timing-accurate ISS
• Debugger (gdb)
• When co-simulation
• The host use inter-process connection (IPC) to
  exchange information

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SystemC Co-simulation

• Use SystemC
• To eliminate overhead between differ simulators

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Co-simulation Methodology

• Full-SystemC
• Need SystemC model of Core
• Cycle-accurate waste simulation time
• Without IPC overhead

• Embedded ISS
• Need bus wrapper to translate ISS information
• Bottleneck on IPC

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Proposed Methods

• To reduce IPC primitive, we proposed
• Triggered co-simulation
• If IPC overhead is slight
• If ISS cant embedded into SystemC simulator
• Legacy co-simulation
• If IPC overhead is serious
• If ISS can embedded into SystemC simulator

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Triggered Co-simulation (TCS)

• Use DDD (Data Display Debugger) package
  encapsulated in gdbAgent class
• UNIX pipes create to send/receive gdb command

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Granularity of TCS

• Coarsest granularity use breakpoint
• Finest granularity use next instruction step by
  step

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Legacy Co-simulation (LCS) (I)

• Transform ISS into C class

wrapper
MEM
Bus
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Legacy Co-simulation (LCS) (II)

• Granularity decided by wait() call

wrapper
MEM
ISS class
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Experimental Platform

• Arbitration strategy
• Aged priority priority decreased as memory
  access increased
• Use semaphore to synchronize processors accessing
  shared memory (RAM)
• Use DLX (simplified MIPS) processor, GNU
  cross-compiler (gcc 2.95.3), and cross debugger
  (gdb version5)

Pin Name Description
rwIn Read/Write
csIn Chip Select
address Address Bus
data Data Bus
ack Acknowledge
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Experimental Setting

• Full-SystemC
• All block implemented by SystemC modules
• Synchronized by clock, read inst. from ROM
• Triggered co-simulation
• Cores replaced by GDBAgent classes
• Processors synchronized by data modified in
  shared memory
• Legacy co-simulation
• Cores replaced by CPU classes
• synchronized by data modified in shared memory

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Experimental Results

• Host
• Pentium II400, 256MB memory, running Linux Red
  Hat 7.2
• For 1 iteration execute more than 2,000
  instructions

Legacy Full-SystemC Triggered
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Conclusions

• SystemC have advantage on single language HW/SW
  co-simulation (in early design flow)
• Speedup simulation by reducing IPC overhead
• Legacy co-simulation need to get modifiable ISS
  source

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Question

• In this paper, why the legacy co-simulation get
  better simulation time than triggered
  co-simulation?