Chapter 5 Problems

1
Chapter 5 Problems
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• Animate the transistor-by-transistor operation of
  the D-latch of Figure 5-2 show which transistors
  are active and how data flows though the circuit
  first CK1, then CK0.
• Draw a stick diagram for a two-input multiplexed
  latch.Place the two transmission gates
  side-by-side.
• Draw a stick diagram for a latch with one data
  input and one reset input, where the reset input
  resets the output to 0. This latch be designed
  ad s multiplexed latch with one constant data
  input.
• Draw a circuit diagram for a D-type master-slave
  flip-flop with a clear input based on the circuit
  of Figure 5-11.
• Draw a circuit diagram for T-type master-slave
  flip-flop based on the circuit of Figure 5-12.
• Redesign the hierarchical stick diagram of the
  counter call to use the resettable latch.
• Do the two phase of a two-phase, non-overpapping
  clock have to be of equal length?

3

• What is the maximum allowable skew as predicted
  by the Hatamian and Cash constructions for these
  parameter valuesT10ns,
• What is the minimum allowable clock
  period under that value of skew?
• Design the system block diagram and one-bit cell
  for a conditional couter, which counts only when
  its input count1.
• Write the state transition table for an eight-bit
  conditional counter. It has two inputs, sount and
  reset(which returns the counter to the 0 count),
  and a three-bit binary output of the current.
• Determine the present state, next state, and
  output of the 01- string recognizer machine for
  the input 10010101110. Assume the machine starts
  in state bit1.
• How can you determine which wire in the
  standard-cell layout of the 10-string
  recognizer is and which is simply
  by looking at the layout?

4

• Write a state transition table for the counter of
  the traffic light controller, assuming that the
  short timeout occurs four clock cycles after the
  counter is reset and that the long timeout occurs
  several clock cycles after reset.
• Consider a two-phase sequential system in which
  all the combinational logic is connected between
  the outputs of the latches and the inputs
  of the latches.
• Draw a two-clocked block diagram of such a
  machine.
• Draw two such systems, connected so that outputs
  of one feed the inputs of the next. Does this
  system satisfy the two-phase clocking discipline
  requirements? Explain.
• Draw a transistor schematic for a master-slave
  flip-flop built from clocked inverters.
• Develop a sequence of tests for the 01-string
  recognizer which tests every combinational gate
  for both stuck-at-0 and stuck-at-1 fault.

5

• Modify the 01-string recognizer, adding one
  primary input and appropriate changes to the
  logic, to significantly shorten the test sequence
  for the machine.
• Generate a set of combinational tests for the
  01-string recognizer which test for all
  stck-at-0/1 faults.
• Generate a set of sequential tests for the
  01-string recognizer which test for all
  stick-at-0/1 faults, assuming you dont know the
  machines initial state.
• Design a stick diagram for the LSSD latch of
  Figure 5-41.