On Reliable Modular Testing with Vulnerable Test Access Mechanisms

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On Reliable Modular Testing with Vulnerable Test
Access Mechanisms

• Lin Huang, Feng Yuan and Qiang Xu

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Purpose

• Is on-chip data transmission reliable?
• What is the solution?
• Correction
• Retransmission
• Hybrid schemes
• They are helpful in normal functional mode
• However, how about modular testing?

Cross talk
Yield loss
IR drop
Yield loss
and even alpha particle hits
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Agenda

• Introduction to Modular Testing
• Test Data Transmission Error-Free Assumption
• Impact of Fault-Tolerant Schemes
• The Proposed Solution
• Jitter-Aware Test Wrapper Design
• Jitter-Transparent ATE Interface Design
• Experimental Results
• Conclusion

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Introduction to Modular Testing

• Divide and conquer manner
• test wrapper
• test access mechanisms (TAMs)
• ATE Interface basic
• TAM designs classification
• dedicated bus-based access scheme
• functional access scheme

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Reuse On-Chip Network as TAM
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Error-Free Assumption is Questionable

• Existing work assumes test data transmission to
  be error-free
• It is questionable when at-speed functional
  interconnects are reused as TAMs

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Fault Tolerance Schemes

• Retransmission and hybrid schemes are mainstream
  techniques to achieve fault-tolerant
  communication
• Retransmission brings problems
• Test traffic jitter
• Test bandwidth mismatch

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The Impact of Retransmission Scheme
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The Significance of These Problems

• Given the number of flits in the entire test data
  volume , the flit error rate , the
  potential yield loss can be expressed as
• When and flit size is 32 bits, the test
  yield loss for the chip containing 21.5M gates
  1 is

11.47 !
1 C. Barnhart et al, Extending OPMISR Beyond
10x Scan Test Efficiency.
IEEE Design Test of Computers, 19(5)65-73,
Sep.-Oct. 2002
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Buffer-Only Solution

• Given the flit injection rate is 0.1 flits per
  cycleand the extra delay caused by one
  retransmission is 40 cycles

st
The
1
nd
The
2
retransmission
retransmission
Shortage of
reserved flits
5
reserved flits
1
reserved flits
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Jitter-Aware Test Wrapper Design

• Two extra states
• HALTIN
• HALTOUT

Input
HALT
IN
Blocked
CAPTRUE
SHIFT
Output
Blocked
HALT
OUT
IEEE 1500
Finite State Machine
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Wrapper Architecture
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Control Logic of Test Wrapper
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Jitter-Transparent ATE Interface

• If the ATE operate in a stream mode
• Minimum buffer size that is able to tolerate the
  extra delay caused by one retransmission
• Given the flit error rate and the number of
  flits , the test yield loss can be computed as
  follows

Without Buffer
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Jitter-Transparent ATE Interface

• We propose to divide the entire input test data
  flow into segments and insert a small section
  of dont-care bits

Data transmission direction
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Test Yield Improvement

• Given the flit error rate , the number of
  flits , and the number of segments , the
  test yield loss can be computed as follows

Without Buffer
With Minimum Buffer Size
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Experimental Setup

• Commercial 90nm CMOS technology
• Area overhead
• 838 two-input NAND equivalent gates
• An industrial circuit 2
• Number of gates 2.6M
• Number of scan cells 274K
• Compressed scan test data volume 106M
• System parameters
• Flit injection rate 0.25 flit per cycle
• Flit size 32 bits
• Retransmission delay 40 cycles

2 C. Barnhart et al, OPMISR The Foundation for
Compressed ATPG Vectors.
In Proc. IEEE International Test Conference, pp.
748-757, Nov. 2001
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Test Yield Loss for a Core with 2.6M Gates
Flit Error Rate 10-7
Yield Loss 28.20
Cost Testing Time Penalty 0.15
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Proposed Technique vs. Buffer-Only Solution
nb Buffer size for buffer-only solution
? Flit error rate
np Buffer size for the proposed design
?Tp Testing time extension ratio of the
proposed design
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Conclusion

• The error-free assumption of existing work is
  questionable
• Fault-tolerant schemes may lead to traffic jitter
  and variable test bandwidth
• We propose a jitter-aware test wrapper and an
  on-chip jitter-transparent ATE interface to
  achieve reliable modular testing
• Experimental results demonstrate the effectiveness

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Thank you !
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Timing Diagram of Test Wrapper