Title: General Logic Design
1General Logic Design
- Dr. Nagesh Tamarapalli, PMTS, AMD India
2Sequential Circuits
- Output depends on current input and past history
of inputs - Circuit holds state that represents memory of
past inputs - State is used to generate current output based on
current input - State variables, one or more bits of information
that forms the state machine
3Describing sequential circuits
- State table
- For each current state specify next state as
function of inputs - Next state F ( current state , input )
- For each current state specify outputs as
function of inputs - Output G ( current state , input )
- State Diagram
- Graphical version of state table
4Clocked synchronous seq. circuits
- Also called state machines of finite state
machines FSM - Use edge triggered flip-flops
- All flip-flops are triggered from the same master
clock signal and therefore all change state
together
5State machine structure ( Moore )
6State machine structure ( Mealy )
7State machine structure ( pipelined )
- Often used in PLD based state machines
- Outputs taken directly from flip-flops, valid
sooner after clock edge - But the output logic must determine output value
one clock tick sooner (pipelined)
8Notation, characteristic equations
- Q means the next value of Q.
- Excitation is the input applied to a device
that determines the next state. - Characteristic equation specifies the next
state of a device as a function of its
excitation. - S-R latch Q S R Q
- Edge-triggered D flip-flop Q D
9Characteristic Equations of latches and flipflops
10Concept of a State Machine
- Depends on history
- State diagram
- State Transition Table
- Next State
- O/P Function
- Timing in State Machines
- State Time
- O/P Validity
- Output is 1 when ever odd sequence of 1s are
detected
11Concept of a State Machine
- Basic Design Approach
- Understand the problem
- Obtain a representation of the FSM
- Perform State Minimization
- Perform state assignment
- Choose FFs
- Important the FSM
State Time
clk
Input
Output
12Example
- To detect a sequence 110011 is a serial bit
stream. - Overlapping sequences are allowed
- Approach
- Think in terms of functionality, not in terms of
Hardware - Get the functionality right, then think about
HardWare - Functionality captured through a state diagram
- Sequence of events important, A FSM can remember
the sequence due to presence of memory. - Combinational circuits cannot remember sequence
13Concept of the Synchronous Sequential Circuit
Example Odd Parity Checker
Assert output whenever input bit stream has odd
of 1's
Reset
0
Even
0
1
Symbolic State Transition Table
1
Odd
1
0
State Diagram
Encoded State Transition Table
14Concept of the Synchronous Sequential Circuit
Example Odd Parity Checker
Next State/Output Functions
NS PS xor PI OUT PS
Input
Output
NS
T
Q
Input
CLK
D
Q
PS/Output
CLK
Q
R
Q
R
\Reset
\Reset
T FF Implementation
D FF Implementation
Timing Behavior Input 1 0 0 1 1 0 1 0 1 1 1 0
15Diagram
1
0
0
S1
S2
S3
S4
S5
S6
I
0
1
1
1
1
1
1
1
0
0
0
16Example
- In a serial communication channel (X-
transmiting) - all seq of 1s are of odd length,
- all seq of zero are of even length under normal
operation - Problem
- To design a circuit that outputs a 1 whenever
there is a violation of above rule, i.e.
discrepancy is observed. - Approach
- Required o/p 1 when sequence of even 1s or
odd Øs
17Example
- In a serial communication channel (X-
transmiting) - all seq of 1s are of odd length,
- all seq of zero are of even length under normal
operation - Problem
- To design a circuit that outputs a 1 whenever
there is a violation of above rule, i.e.
discrepancy is observed. - Approach
- Required o/p 1 when sequence of even 1s or
odd Øs
- 4 possible states (min)
- ----- Odd 1 ?---- Odd Ø
- ?------ Even 1 ?---- Even Ø
18Diagram
Reset
Odd 1
Even 1
Odd Ø
Even Ø