ELEN 468 Advanced Logic Design

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ELEN 468Advanced Logic Design

• Lecture 7
• System Tasks, Functions, Syntax
• and Behavioral Modeling I

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System Tasks and Functions
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Display Tasks

• monitor
• monitor(d f b b, time, realtime, x, y)
• Continuously display values
• display, displayb, displayo, displayh
• display(x b y b, x, y)
• Display once only
• write, writeb, writeo, writeh
• write(x b y b, x, y)
• Same as display, but no \n

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Files

• fopen, fclose, fdisplay

• module test_bench()
• reg x
• wire y
• integer cd
• assign y x
• initial begin
• cd fopen("test.dat")
• 100 x 0
• fdisplay(cd, "b b", x, y)
• fclose(cd)
• end
• endmodule

channel descriptor
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Read Memory
parameter ram_file ram_data_file reg
150 RAM_1 01023 initial
readmemh(ram_file, RAM_1) // read input
file as hexadecimal initial
readmemb(ram_file, RAM_1) // read input
file as binary
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Simulation Control

• finish and finish(n)
• n 0, print nothing
• n 1, print simulation time and location
• n 2, print simulation time, location and
  statistics
• stop(n) interactive mode

initial 200 finish
initial begin 20 x0 y0 stop(0)
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Probability Distribution

• Generate different types of distributions

integer seed, d d dist_uniform(seed, 0,
9) d dist_exponential(seed, 3) d
dist_normal(seed, 0, 5)
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Compiler Directives

• include testbench.v
• defaultnettype wor
• define wait_state 3b010
• undef wait_state
• ifdef BEHAVIORAL
• y x1 x2
• else
• or ( y, x1, x2 )
• endif

• timescale
• include
• defaultnettype
• define and undef
• ifdef, else, endif

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Syntax
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BNF Formal Syntax Notation

• BNF Backus-Naur Form or Backus Normal Form
• definition of syntax
• alternative syntax
• appear once or not at all
• appear any times, or not at all

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Example of Verilog Syntax
source_text description description
module_declaration udp_declaration
module_declaration module_keyword
module_identifier list_of_ports
module_item endmodule module_keyword
module macromodule
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list_of_ports ( port , port )
module_item module_item_declaration
parameter_overwrite continuous_assign
gate_instantiation udp_instantiation
module_instantiation specify_block
initial_construct always_construct
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continuous_assign assign drive_strength d
elay3 list_of_net_assignments drive_strength
( strength0, strength1) delay3
delay_value (delay_value , delay_value ,
delay_value ) list_of_net_assignments
net_assignment , net_assignment
net_assignment net1_value expression
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Behavioral Modeling I
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Structural vs. Behavioral Descriptions
module my_module() assign //
continuous assignment and () //
instantiation of primitive adder_16 M() //
instantiation of module always _at_()
begin end initial begin
end endmodule
Structural, no order
Behavior, in order in each procedure
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Behavioral Descriptions In General

• Co-exists with gate instantiations
• Not all descriptions synthesize
• Not all synthesized descriptions are desirable
• Non-structural behaviors
• Continuous assignment
• initial
• always
• Within a module
• Multiple behaviors are allowed
• Nested behaviors are not allowed

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Behavioral Statements

• initial always
• single_statement
• begin
• block_of_statements
• end

• initial
• Activated from tsim 0
• Executed once
• Initialize a simulation
• always
• Activated from tsim 0
• Executed cyclically
• Continue till simulation terminates

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Example of Behavioral Statement

• module clock1 ( clk )
• parameter half_cycle 50
• parameter max_time 1000
• output clk
• reg clk
• initial
• clk 0
• always
• begin
• half_cycle clk clk
• end
• initial
• max_time finish
• endmodule

clk
50
100
150
200
tsim
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Assignment

• Continuous assignment
• Values are assigned to net variables due to some
  input variable changes
• assign
• Procedural assignment
• Values are assigned to register variables when
  certain statement is executed in a behavior
• Procedural assignment,
• Procedural continuous assignment, assign
  deassign
• Non-blocking assignment, lt

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Blocking and Non-blocking Assignment

• initial
• begin
• a 1
• b 0
• a b // a 0
• b a // b 0
• end
• initial
• begin
• a 1
• b 0
• a lt b // a 0
• b lt a // b 1
• end

• Blocking assignment
• Statement order matters
• A statement has to be executed before next
  statement
• Non-blocking assignment lt
• Concurrent assignment
• If there are multiple non-blocking assignments to
  same variable in same behavior, latter overwrites
  previous

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Procedural Continuous Assignment

• Continuous assignment establishes static binding
  for net variables
• Procedural continuous assignment (PCA)
  establishes dynamic binding for variables
• assign deassign for register variables only
• force release for both register and net
  variables

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assign deassign PCA

• module flop ( q, qbar, preset,
• clear, clock, data )
• assign qbar q
• initial
• q 0
• always _at_ ( negedge clk )
• q data
• always _at_ ( clear or preset )
• begin
• if ( !preset ) assign q 1
• else if ( !clear ) assign q 0
• else deassign q
• end
• endmodule

• Binding takes effect when PCA statement is
  executed
• Can be overridden by another PCA statement
• deassign is optional
• assign takes control, deassign release
  control
• PCA overwrites procedural assignments

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Example of assign
module mux4_PCA(a, b, c, d, select, y_out)
input a, b, c, d input 10 select output
y_out reg y_out always _at_(select) begin
if (select 0) assign y_outa else
if (select 1) assign y_outb else if
(select 2) assign y_outc else if
(select 3) assign y_outd else assign
y_out1bx end endmodule
y_out changes with a
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Alternative
module mux4_PCA(a, b, c, d, select, y_out)
input a, b, c, d input 10 select output
y_out reg y_out always _at_(select or a or b or
c or d) begin if (select 0)
y_outa else if (select 1) y_outb
else if (select 2) y_outc else if
(select 3) y_outd else y_out1bx
end endmodule
Value of a is assigned to y_out at this time
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force release PCA

• force sig1 0
• force sig2 1
• Sig3 0
• 9 sig3 1
• release sig1
• release sig2

• Similar to assigndeassign
• Can be applied to net variables
• Often applied in testing

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Comparisons of Assignment
mode mode mode mode mode
Output of primitive Continuous assignment Procedural assignment assign deassign PCA force release PCA
Variable Net Seq-reg Net Register Register Net and register
description Structural Structural Behavioral Behavioral Behavioral
binding Static Static Dynamic, one shot Dynamic, continuous Dynamic, continuous