ELEN 468 Advanced Logic Design

1
ELEN 468Advanced Logic Design

• Lecture 8
• Behavioral Descriptions II

2
Procedural Timing Control

• Delay control
• Event control
• Named events
• wait construct

3
Delay Control Operator ()

• initial
• begin
• 0 in1 0 in2 1
• 10 in3 1
• 40 in4 0 in5 1
• 60 in3 0
• end

4
Event Control Operator (_at_)

• _at_ ( eventA or eventB ) begin
• _at_ ( eventC ) begin
• end
• end

• Event -gt identifier or expression
• When _at_ is reached
• Activity flow is suspended
• The event is monitored
• Other processes keep going
• posedge 0-gt1, 0-gtx, x-gt1
• negedge 1-gt0, 1-gtx, x-gt0
• Cannot assign value to the event variable inside
  the synchronized behavior

5
Named Event

• module modA ()
• event sth_happens // declaration
• always
• -gtsth_happens // trigger event
• end
• endmodule
• module modB()
• always _at_ (top_mod.modA.sth_happens)
• endmodule

• Also called abstract event
• Declared only in module with keyword event
• Must be declared before it is used
• Event is triggered by -gt
• Provide high level inter-module communication
  without physical details

6
Example of Named Event

• module flop_event ( clk, reset, data, q, q_bar )
• input clk, reset, data
• output q, q_bar
• reg q
• event up_edge
• assign q_bar q
• always _at_ ( posedge clk ) -gt up_edge
• always _at_ ( up_edge or negedge reset )
• begin
• if ( reset 0 ) q 0 else q data
• end
• endmodule

7
The wait Construct

• module modA ()
• always
• begin
• wait ( enable ) ra rb
• end
• endmodule

• Activity flow is suspended if expression is false
• It resumes when the expression is true
• Other processes keep going

8
Intra-assignment Delay Blocking Assignment

• // B 0 at time 0
• // B 1 at time 4
• 5 A B // A 1
• C D
• A 5 B // A 0
• C D
• A _at_(enable) B
• C D
• A _at_(named_event) B
• C D

• If timing control operator(,_at_) on LHS
• Blocking delay
• RHS evaluated at (,_at_)
• Assignment at (,_at_)
• If timing control operator(,_at_) on RHS
• Intra-assignment delay
• RHS evaluated immediately
• Assignment at (,_at_)

9
Intra-assignment Delay Non-blocking Assignment

• In 1st cycle, acc is sampled
• What if no bus change in the same cycle?
• In next cycle, acc is sampled again
• Value of acc from previous cycle is overwritten
• Warning message

• always begin
• _at_ ( posedge clk )
• G lt _at_ (bus) acc
• C lt D // not blocked
• end

• Sampling RHS immediately in the latest cycle
• Wait for time control to execute assignment
• Subsequent assignments are not blocked

10
Be Cautious

• module or8( y, a, b )
• input 70 a, b
• output 70 y
• reg 70 y
• initial begin
• assign y a b
• end
• endmodule

• Model combinational logic by one-shot (initial)
  behavior
• Valid
• Not preferred
• Not accepted by synthesis tool

11
Example
initial begin a 10 1 b 2 0 c 3 1
end initial begin d lt 10 1 e lt 2 0 f lt
3 1 end
t a b c d e f 0 x x x x x x 2 x x x x 0 x
3 x x x x 0 1 10 1 x x 1 0 1 12 1 0 x 1 0 1 15
1 0 1 1 0 1
12
Tell the Differences
always _at_ (a or b) y ab always _at_ (a or
b) 5 y ab always _at_ (a or b) y 5
ab always _at_ (a or b) y lt 5 ab
Which one describes or gate?
13
Simulation of Assignments

• For each given time step
• Evaluate all Right-Hand-Side
• Execute blocking assignment
• Execute non-blocking assignment that do not have
  intra-assignment timing control
• Execute past non-blocking assignment that is
  scheduled at this time
• Execute monitor. However, display is executed
  whenever it is encountered.
• Increment time step

14
Simulation of Non-blocking Assignment

• Normally the last assignment at certain
  simulation time step
• If it triggers other blocking assignments, it is
  executed before the blocking assignment it
  triggers

• always
• begin
• A lt B
• end
• always
• begin
• C _at_(A) D
• end

15
Example
initial begin a 1 b 0 a lt b
b lt a display(ab bb, a,
b) end
initial begin a 1 b 0 a lt b
b lt a monitor(ab bb, a,
b) end
a1 b0
a0 b1
16
Repeated Intra-assignment Delay

• regA repeat (5) _at_ ( negedge clk ) regB

• begin
• tmp regB
• _at_ ( negedge clk )
• _at_ ( negedge clk )
• _at_ ( negedge clk )
• _at_ ( negedge clk )
• _at_ ( negedge clk )
• regA tmp
• end

17
Indeterminate Assignment

• module multi_assign()
• reg a, b, c, d
• initial begin
• 5 a 1 b 0 end
• always _at_ ( posedge a ) begin
• c a
• end
• always _at_ ( posedge a ) begin
• c b
• end
• always _at_ ( posedge a ) begin
• d b
• end
• always _at_ ( posedge a ) begin
• d a
• end
• endmodule

• Multiple assignments are made to same variable in
  different behavior
• Value depends on code order or vendor
  specifications
• Similar to race-conditions in hardware