Logic synthesis from concurrent specifications

1
Logic synthesis from concurrent specifications

• Jordi Cortadella
• Universitat Politecnica de CatalunyaBarcelona,
  Spain

In collaboration with M. Kishinevsky, A.
Kondratyev, L. Lavagno and A. Yakovlev
2
Outline

• Overview of the synthesis flow
• Specification
• State graph and next-state functions
• State encoding
• Implementability conditions
• Speed-independent circuit
• Complex gates
• C-element architecture
• Review of some advanced topics

3
Book and synthesis tool

• J. Cortadella, M. Kishinevsky, A. Kondratyev,L.
  Lavagno and A. Yakovlev,Logic synthesis for
  asynchronouscontrollers and interfaces,Springer-
  Verlag, 2002
• petrifyhttp//www.lsi.upc.es/petrify

4
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
5
Specification
x
x
y
y
z
z
x-
z
x
y
z-
y-
Signal Transition Graph (STG)
6
Token flow
7
State graph
8
Next-state functions
9
Gate netlist
x
y
z
10
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
11
VME bus
Bus
Data Transceiver
Device
D
LDS
DSr
VME Bus Controller
DSw
LDTACK
DTACK
12
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
13
Choice Read and Write cycles
DSr
DSw
LDS
D
LDTACK
LDS
D
LDTACK
DTACK
D-
DSr-
DTACK
D-
DSw-
14
Choice Read and Write cycles
15
Circuit synthesis

• Goal
• Derive a hazard-free circuitunder a given delay
  model andmode of operation

16
Speed independence

• Delay model
• Unbounded gate / environment delays
• Certain wire delays shorter than certain paths in
  the circuit
• Conditions for implementability
• Consistency
• Complete State Coding
• Persistency

17
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
18
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
19
Binary encoding of signals
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
20
Binary encoding of signals
DSr
DTACK-
10000
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
10010
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
10110
01110
10110
D
D-
DSr-
DTACK
(DSr , DTACK , LDTACK , LDS , D)
21
Excitation / Quiescent Regions
22
Next-state function
0 ? 1
0 ? 0
1 ? 1
1 ? 0
23
Karnaugh map for LDS
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
24
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
25
Concurrency reduction
LDS
LDS-
LDS-
LDS-
10110
10110
26
Concurrency reduction
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
27
State encoding conflicts
LDS
LDTACK-
LDS-
LDTACK
10110
10110
28
Signal Insertion
LDTACK-
LDS
LDS-
LDTACK
101101
101100
D-
DSr-
29
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
30
Complex-gate implementation
31
Implementability conditions

• Consistency
• Rising and falling transitions of each signal
  alternate in any trace
• Complete state coding (CSC)
• Next-state functions correctly defined
• Persistency
• No event can be disabled by another event (unless
  they are both inputs)

32
Implementability conditions

• Consistency CSC persistency
• There exists a speed-independent circuit that
  implements the behavior of the STG(under the
  assumption that ay Boolean function can be
  implemented with one complex gate)

33
Persistency
a
c
b
is this a pulse ?
Speed independence ? glitch-free output behavior
under any delay
34
(No Transcript)
35
ER(d)
ER(d-)
36
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Complex gate
37
Implementation with C elements
? S ? z ? S- ? R ? z- ? R- ?

• S (set) and R (reset) must be mutually exclusive
• S must cover ER(z) and must not intersect
  ER(z-) ? QR(z-)
• R must cover ER(z-) and must not intersect
  ER(z) ? QR(z)

38
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
S
d
C
R
39
but ...
S
d
C
R
40
Starting from state 0000 (R1 and S0)
a R- b a- c S d
S
d
C
R
41
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Monotonic covers
42
C-based implementations
c
d
C
b
a
c
weak
c
d
weak
d
a
a
b
generalized C elements (gC)
43
Speed-independent implementations

• Implementability conditions
• Consistency
• Complete state coding
• Persistency
• Circuit architectures
• Complex (hazard-free) gates
• C elements with monotonic covers
• ...

44
Synthesis exercise
1011
0011
0111
Derive circuits for signals x and z (complex
gates and monotonic covers)
45
Synthesis exercise
1011
wx
yz
00
01
11
10
-
1
1
0
00
0011
-
1
1
0
01
-
0
0
0
11
-
1
1
0
10
0111
Signal x
46
Synthesis exercise
1011
wx
yz
00
01
11
10
-
0
0
0
00
0011
-
0
0
0
01
-
1
1
1
11
-
1
0
0
10
0111
Signal z
47
Logic decomposition example
y-
y-
1001
1011
z-
w-
1000
0001
w
y
x
w-
z-
z-
w-
w
1010
0000
0101
0011
w-
z-
y
x
y
x
x-
0010
0100
x-
y
x
z
0110
0111
z
48
Logic decomposition example
x
y-
w
y
1001
1011
z-
z
w-
y
1000
0001
w
y
z
x
w-
z-
x
w
1010
0000
0101
0011
w-
z-
y
x
w
y
z
0010
0100
x-
z
y
x
z
y
0110
0111
x
z
y
49
Logic decomposition example
s1
x
y-
w
s
1001
1011
y
z-
s-
z
w
1001
1000
z-
s-
y
w-
x
w
0011
0001
1000
1010
y
s-
x
w-
z-
w
x-
y
z
0000
0101
1010
z
w-
z-
y
x
0111
0010
0100
y
s
y
x
x
z
s0
z
0111
y
0110
50
Logic decomposition example
s1
y-
y-
1001
1011
z-
s-
s-
w
1001
1000
z-
s-
y
w-
z-
w-
w
0011
0001
1000
1010
y
s-
x
w-
z-
x-
0000
0101
1010
y
x
x-
w-
z-
y
x
0111
0010
0100
s
s
y
x
z
s0
z
0111
0110
51
Speed-independent Netlist
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
52
Adding timing assumptions
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
53
Adding timing assumptions
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
54
State space domain
DSr
LDTACK-
55
State space domain
DSr
LDTACK-
56
State space domain
DSr
LDTACK-
Two more unreachable states
57
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
58
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
One more DC vector for all signals
One state conflict is removed
59
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
60
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
DSr
LDTACK
61
Conclusions

• STGs have a high expressiveness power at a low
  level of granularity (similar to FSMs for
  synchronous systems)
• Synthesis from STGs can be fully automated
• Synthesis tools often suffer from the state
  explosion problem (symbolic techniques are used)
• The theory of logic synthesis from STGs can be
  found in

J. Cortadella, M. Kishinevsky, A. Kondratyev, L.
Lavagno and A. Yakovlev,Logic Synthesis of
Asynchronous Controllers and Interfaces,Springer
Verlag, 2002.