Introduction to asynchronous circuit design: specification and synthesis

1
Introduction toasynchronous circuit design
specification and synthesis

• Part III
• Advanced topics on synthesis of control circuits
  from STGs

2
Outline

• Logic decomposition
• Hazard-free decomposition
• Signal insertion
• Technology mapping
• Optimization based on timing information
• Relative timing
• Timing assumptions and constraints
• Automatic generation of timing assumptions

3
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
4
No Hazards
5
Decomposition May Lead to Hazards
1000
1100
1100
0100
0110
6
Decomposition

• Acknowledgement
• Global acknowledgement
• Generating candidates
• Hazard-free signal insertion
• Event insertion
• Signal insertion

7
Global acknowledgement
8
How about 2-input gates ?
9
How about 2-input gates ?
c
z
b
a
a
y
b
d
10
How about 2-input gates ?
0
c
0
z
b
a
a
y
b
d
11
How about 2-input gates ?
c
z
b
a
a
y
b
d
12
How about 2-input gates ?
c
z
y
d
13
Strategy for logic decomposition

• Each decomposition defines a new internal signal
  
• Method Insert new internal signals such that
• After resynthesis, some large gates are
  decomposed
• The new specification is hazard-free
• Generate candidates for decomposition using
  standard logic factorization techniques
• Algebraic factorization
• Boolean factorization (boolean relations)

14
Decomposition example
15
y-
1001
1011
z-
w-
1000
0001
w
y
x
w-
z-
1010
0000
0101
0011
w-
z-
y
x
0010
0100
x-
y
x
z
0110
0111
16
s1
y-
s
1001
1011
z-
s-
w
1001
1000
z-
s-
y
w-
0011
0001
1000
1010
y
s-
x
w-
z-
x-
0000
0101
1010
w-
z-
y
x
0111
0010
0100
s
y
x
s0
z
0111
0110
17
s1
y-
y-
1001
1011
z-
s-
s-
w
1001
1000
z-
s-
y
w-
z-
w-
w
0011
0001
1000
1010
y
s-
x
w-
z-
x-
0000
0101
1010
y
x
x-
w-
z-
y
x
0111
0010
0100
s
s
y
x
z
s0
z
0111
0110
18
y-
1011
z-
w-
1000
0001
w
y
x
w-
z-
1010
0000
0101
0011
w-
z-
y
x
0010
0100
x-
y
x
z
0110
0111
yz1
yz0
19
y-
y-
s1
1001
1011
s-
s-
w
1001
z-
w-
0011
0001
1000
z-
w-
w
y
x
w-
z-
x-
0000
0101
1010
w-
z-
y
x
y
x
x-
0111
0010
0100
s
y
x
s
s0
z
z
0111
0110
z- is delayed by the new transition s- !
20
y-
s1
1001
1011
s-
w
1001
z-
w-
0011
0001
1000
y
x
w-
z-
x-
0000
0101
1010
w-
z-
y
x
0111
0010
0100
s
y
x
y
y
y
y
y
y
y
s0
z
0111
0110
21
Decomposition (Algebraic, Boolean relations)
F
22
Decomposition (Algebraic, Boolean relations)
F
until no more progress
Hazard-free ? (Event insertion)
23
Signal insertion for function F
Insertion by input borders
State Graph
24
Event insertion
25
Event insertion
SR(x)
b
x
x
x
x
26
Properties to preserve
a is persistent
27
Boolean decomposition
f F (x1,,xn)
f G(H(x1,,xn))
Our problem Given F and G, find H
28
h1
f
h2
This is a Boolean Relation
29
a
F
c
y
d
30
a
c
y
d
31
a
c
y
d
a
32
a
c
y
d
a
d
c
33
Technology mapping

• Merging small gates into larger gates introduces
  no new hazards
• Standard synchronous technique can be applied,
  e.g. BDD-based boolean matching
• Handles sequential gates and combinational
  feedbacks
• Due to hazards there is no guarantee to find
  correct mapping (some gates cannot be decomposed)
• Timing-aware decomposition can be applied in
  these rare cases

34
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
35
Timing assumptions in design flow

• Speed-independent wire delays after a
  forksmaller than fan-out gate delays
• Burst-mode circuit stabilizes betweentwo
  changes at the inputs
• Timed circuits Absolute bounds on gate /
  environment delays are known a priori (before
  physical design)

36
Relative Timing Circuits

• Assumptions a before b
• for concurrent events reduces reachable state
  space
• for ordered events permits early enabling
• both increase dont care space for logic
  synthesis gt simplify logic (better area and
  timing)
• Assume - if useful - guarantee approach
  assumptions are used by the tool to derive a
  circuit and required timing constraints that must
  be met in physical design flow
• Applied to design of the Rotating Asynchronous
  Pentium Processor(TM) Instruction Decoder
  (K.Stevens, S.Rotem et al. Intel Corporation)

37
Relative Timing Asynchronous Circuits
Speed-independent C-element
b
c
a
38
State Graph (Read cycle)
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
39
Lazy Transition Systems
ER (LDS)
LDS
LDS-
LDS-
LDS-
FR (LDS-)
DTACK-
ER (LDS-)
Event LDS- is lazy firing subset of enabling
40
Timing assumptions

• (a before b) for concurrent events
  concurrency reduction for firing and
  enabling
• (a before b) for ordered events
  early enabling
• (a simultaneous to b wrt c) for triples of
  events combination of the above

41
Speed-independent Netlist
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
42
Adding timing assumptions (I)
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
43
Adding timing assumptions (I)
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
44
State space domain
DSr
LDTACK-
45
State space domain
DSr
LDTACK-
46
State space domain
DSr
LDTACK-
Two more unreachable states
47
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
48
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
One more DC vector for all signals
One state conflict is removed
49
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
50
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
51
Timing assumptions

• (a before b) for concurrent events
  concurrency reduction for firing and
  enabling
• (a before b) for ordered events
  early enabling
• (a simultaneous to b wrt c) for triples of
  events combination of the above

52
Ordered events early enabling
b
b
a
c
c
F
G
a
b
c
53
Adding timing assumptions (II)
DSr
DTACK-
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
DSr
LDTACK
54
State space domain
LDS-
D-
DSr-
Reachable space is unchanged
For LDS- enabling can be changed in one state
55
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
56
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
-
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
One more DC vector for one signal LDS
If used LDS DSr, otherwise LDS DSr D
57
Before early enabling
DSr
DTACK-
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
DSr
LDTACK
58
Netlist with two constraints
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
DSr
LDS
LDTACK
Both timing assumptions are used for optimization
and become constraints
59
Deriving automatic timing assumptions

• Rule I (out of 6) a,b - non-input events
• Untimed ordering ab and a enabled before b,
  but not vice versa
• Derived assumption a fires before b
• Justification delay of a gate can be made
  shorter than delay of two (or more) gates del(a)
  lt del(c)del(b)

c
b
a
a
a
c
b
b
60
Deriving automatic timing assumptions

• Rule I (out of 6) a,b - non-input events
• Untimed ordering (ab) and (a enabled before
  b), but not vice versa
• Derived assumption a fires before b
• Justification delay of a gate can be made
  shorter than delay of two (or more) gates

c
b
a
a
a
c
b
b

• Effect I a state becomes DC for all signals

61
Deriving automatic timing assumptions

• Rule I (out of 6) a,b - non-input events
• Untimed ordering (ab) and (a enabled before
  b), but not vice versa
• Derived assumption a fires before b
• Justification delay of a gate can be made
  shorter than delay of two (or more) gates

c
b
a
a
a
c
b
b

• Effect II another state becomes local DC for
  signal of event b

62
Backannotation of Timing Constraints

• Timed circuits require post-verification
• Can synthesis tools help ?
• Report the least stringent set of timing
  constraints required for the correctness of the
  circuit
• Not all initial timing assumptions may be
  required
• Petrify reports a set of constraints for order of
  firing that guarantee the circuit correctness

63
Timing constraints generation
a
c
b
d
d
d
d
b
c
a
e
e
e
c
b
Assumptions d before b and c before e and a
before d
64
Timing constraints generation
a
c
b
d
d
d
d
b
c
a
e
e
e
c
b
Assumptions d before b and c before e and a
before d
65
Timing constraints generation
a
c
b
d
d
d
d
b
c
a
e
e
e
c
b
Assumptions d before b and c before e and a
before d
66
Timing constraints generation
1
a
c
b
d
d
d
d
b
c
a
Incorrect behavior
e
e
e
c
b
2
Assumptions d before b and c before e and a
before d
67
Covering incorrect behavior
3
1
a
c
b
d
d
d
d
b
c
a
5
e
e
e
c
b
2
4
Assumptions d before b and c before e and a
before d
Other possible constraints remove states from
assumption domain gt invalid
68
Covering incorrect behavior
3
1
a
c
b
d
d
d
d
b
c
a
5
c before e
e
e
e
c
b
2, 4
2
4
Assumptions d before b and c before e and a
before d
Constraints for the minimal cost solution d
before c and c before e
69
Timing aware state encoding

• Solve only state conflicts reachable in the RT
  assumptions domain
• Generate automatic timing assumptions for
  inserted state signals gt state signals can be
  implemented as RT logic
• State variables inserted concurrently with I/O
  events gt latency and cycle time reduction

70
Value of Relative Timing

• RT circuits provides up to 2-3x (1.3-2x)
  delayarea reduction with respect to SI circuits
  synthesized without (with) concurrency reduction
• Automatic generation of timing assumptions gt
  foundation for automatic synthesis of RT circuits
  with area/performance comparable/better than
  manual
• Back-annotation of timing constraints gt minimal
  required timing information for the back-end
  tools
• Timing-aware state encoding allows significant
  area/performance optimization

71
Design Flow with Timing
Specification(STG user assumptions)
Reachability analysis
Lazy State Graph
Timing-aware state encoding
Automatic Timing Assumptions
Lazy SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Required Timing Constraints
Gate netlist
72
FIFO example
ro
li
FIFO
lo
ri
73
Speed-Independent Implementation
without concurrency reduction 3 state signals are
required
74
SI implementation with concurrency reduction
x
li
ro-
lo-
ri-
ri
li
-

gC
x
gC

ro
lo
li-
lo
ro
ri
x-
75
RT implementation
ri
li
x
lo
ro
76
RT implementation
x
li
lo-
ro-
ri-
To satisfy the constraint Delay(x- ) lt Delay
(ri )
and Delay(lo) Delay(x- ) lt Delay(ro ) Delay
(ri )
li-
lo
ro
ri
x-
All constraints are either satisfied by default
or easy to satisfy by sizing