Introduction to asynchronous circuit design: specification and synthesis

1
Introduction toasynchronous circuit design
specification and synthesis

• Part II
• Synthesis of control circuitsfrom STGs

2
Outline

• Overview of the synthesis flow
• Specification
• State graph and next-state functions
• State encoding
• Implementability conditions
• Speed-independent circuit
• Complex gates
• C-element architecture

3
Design flow
4
x
x
y
y
z
z
x-
z
x
y
z-
y-
Signal Transition Graph (STG)
5
(No Transcript)
6
(No Transcript)
7
Next-state functions
8
x
y
z
9
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
10
VME bus
11
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
12
Choice Read and Write cycles
13
Choice Read and Write cycles
14
Choice Read and Write cycles
15
Choice Read and Write cycles
16
Circuit synthesis

• Goal
• Derive a hazard-free circuitunder a given delay
  model andmode of operation

17
Speed independence

• Delay model
• Unbounded gate / environment delays
• Certain wire delays shorter than certain paths in
  the circuit
• Conditions for implementability
• Consistency
• Complete State Coding
• Persistency

18
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
19
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
20
Binary encoding of signals
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
21
Binary encoding of signals
DSr
DTACK-
10000
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
10010
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
10110
01110
10110
D
D-
DSr-
DTACK
(DSr , DTACK , LDTACK , LDS , D)
22
Excitation / Quiescent Regions
23
Next-state function
0 ? 1
0 ? 0
1 ? 1
1 ? 0
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Karnaugh map for LDS
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
26
Concurrency reduction
LDS
LDS-
LDS-
LDS-
10110
10110
27
Concurrency reduction
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
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State encoding conflicts
LDS
LDTACK-
LDS-
LDTACK
10110
10110
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Signal Insertion
LDTACK-
LDS
LDS-
LDTACK
101101
101100
D-
DSr-
30
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
31
Complex-gate implementation
32
Implementability conditions

• Consistency
• Rising and falling transitions of each signal
  alternate in any trace
• Complete state coding (CSC)
• Next-state functions correctly defined
• Persistency
• No event can be disabled by another event (unless
  they are both inputs)

33
Implementability conditions

• Consistency CSC persistency
• There exists a speed-independent circuit that
  implements the behavior of the STG(under the
  assumption that ay Boolean function can be
  implemented with one complex gate)

34
Persistency
a
c
b
is this a pulse ?
Speed independence ? glitch-free output behavior
under any delay
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(No Transcript)
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ER(d)
ER(d-)
37
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Complex gate
38
Implementation with C elements
? S ? z ? S- ? R ? z- ? R- ?

• S (set) and R (reset) must be mutually exclusive
• S must cover ER(z) and must not intersect
  ER(z-) ? QR(z-)
• R must cover ER(z-) and must not intersect
  ER(z) ? QR(z)

39
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
S
d
C
R
40
but ...
S
d
C
R
41
Starting from state 0000 (R1 and S0)
a R- b a- c S d
S
d
C
R
42
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Monotonic covers
43
C-based implementations
c
d
C
b
a
c
weak
c
d
weak
d
a
a
b
generalized C elements (gC)
44
Speed-independent implementations

• Implementability conditions
• Consistency
• Complete state coding
• Persistency
• Circuit architectures
• Complex (hazard-free) gates
• C elements with monotonic covers
• ...

45
Synthesis exercise
1011
0011
0111
Derive circuits for signals x and z (complex
gates and monotonic covers)
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Synthesis exercise
1011
wx
yz
00
01
11
10
-
1
1
0
00
0011
-
1
1
0
01
-
0
0
0
11
-
1
1
0
10
0111
Signal x
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Synthesis exercise
1011
wx
yz
00
01
11
10
-
0
0
0
00
0011
-
0
0
0
01
-
1
1
1
11
-
1
0
0
10
0111
Signal z