STG-based synthesis and Petrify

1
STG-based synthesis and Petrify
J. Cortadella (Univ. Politècnica Catalunya)Mike
Kishinevsky (Intel Corporation)Alex Kondratyev
(University of Aizu)Luciano Lavagno (Universitá
di Udine)Enric Pastor (Univ. Politècnica
Catalunya) Alexander Taubin (University of
Aizu) Alex Yakovlev (Univ. Newcastle upon Tyne)
2
What is it about?

• This tutorial is about the synthesis of
  asynchronous circuits from behavioral
  specifications.
• STGs can specify I/O concurrency(based on Petri
  nets).
• STGs specify behavior at a level in which logic
  synthesis techniques can be applied.
• Speed-independent and timed circuits can be
  derived.

3
Design flow
4
Outline

• Overview
• Synthesis steps
• Specification (STGs)
• State encoding
• Logic synthesis, decomposition and mapping
• Synthesis with relative timing
• Conclusions

5
x
x
y
y
z
z
x-
z
x
y
z-
y-
Signal Transition Graph (STG)
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Next-state functions
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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
11
VME bus
12
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
13
Choice Read and Write cycles
14
Choice Read and Write cycles
15
Choice Read and Write cycles
16
Choice Read and Write cycles
17
Circuit synthesis

• Goal
• Derive a hazard-free circuitunder a given delay
  model andmode of operation

18
Modes of operation

• Fundamental mode
• Single-input changes
• Multiple-input changes
• Input / Output mode
• Concurrencycircuit / environment

Currentstate
Nextstate
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Speed independence

• Delay model
• Unbounded gate / environment delays
• Certain wire delays shorter than certain paths in
  the circuit
• Conditions for implementability
• Consistency
• Complete State Coding
• Output persistency

20
Other synthesis approaches

• Burst-mode machines
• Mealy-like FSMs
• Fundamental mode (slow environment)
• VLSI programming
• Syntax-directed translation from
  CSP(Communicating Sequential Processes)
• No logic synthesis
• Circuit size Size of the specification

21
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
22
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
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State Graph (Read cycle)
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
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Binary encoding of signals
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
25
Binary encoding of signals
DSr
DTACK-
10000
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
10010
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
10110
01110
10110
D
D-
DSr-
DTACK
(DSr , DTACK , LDTACK , LDS , D)
26
Excitation / Quiescent Regions
27
Next-state function
0 ? 1
0 ? 0
1 ? 1
1 ? 0
28
Karnaugh map for LDS
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
29
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
30
Concurrency reduction
LDS
LDS-
LDS-
LDS-
10110
10110
31
Concurrency reduction
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
32
State encoding conflicts
LDS
LDTACK-
LDS-
LDTACK
10110
10110
33
Signal Insertion
LDTACK-
LDS
LDS-
LDTACK
101101
101100
D-
DSr-
34
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
35
Complex-gate implementation
36
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
37
Hazards
38
Hazards
1000
1100
1100
0100
0110
39
Decomposition

• Global acknowledgement
• Generating candidates
• Hazard-free signal insertion
• Event insertion
• Signal insertion

40
Global acknowledgement
41
How about 2-input gates ?
42
How about 2-input gates ?
c
z
b
a
a
y
b
d
43
How about 2-input gates ?
0
c
0
z
b
a
a
y
b
d
44
How about 2-input gates ?
c
z
b
a
a
y
b
d
45
How about 2-input gates ?
c
z
y
d
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Strategy for logic decomposition

• Each decomposition defines a new internal signal
  
• Method Insert new internal signals such that
• After resynthesis, some large gates are
  decomposed
• The new specification is hazard-free
• Generation of candidates for decomposition
• Algebraic factorization
• Boolean factorization (boolean relations)

47
Decomposition example
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y-
s
50
s1
y-
s-
s-
s-
s
s0
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s1
y-
y-
1001
1011
s-
w
1001
z-
0011
1000
z-
w-
w
y
x-
1010
y
x
x-
0111
s
s0
z
z
0111
z- is delayed by the new transition s- !
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Signal insertion for function F
Insertion by input borders
State Graph
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Event insertion
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Properties to preserve
a is persistent
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Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Design flow
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
58
Timing assumptions in design flow

• Speed-independent wire delays after a
  forkshorter than fan-out gate delays
• Burst-mode circuit stabilizes betweentwo
  changes at the inputs
• Timed circuits Absolute bounds on gate /
  environment delays are known a priori (before
  physical design)

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Relative Timing Circuits

• Assumptions a before b for concurrent
  andordered events
• Used by the tool to derive a circuit and timing
  constraints that must be met in physical design
  flow
• Applied to design of the Rotating Asynchronous
  Pentium Processor(TM) Instruction Decoder
  (K.Stevens, S.Rotem et al. Intel Corporation)

60
Lazy Transition Systems
ER (LDS)
LDS
LDS-
LDS-
LDS-
FR (LDS-)
DTACK-
EnR (LDS-)
Event LDS- is lazy firing subset of enabling
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Timing assumptions

• (a before b) for concurrent events
  concurrency reduction for firing and
  enabling
• (a before b) for ordered events
  early enabling
• (a simultaneous to b wrt c) for triples of
  events combination of the above

62
Netlist with SI timing constraints
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
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Adding timing assumptions (I)
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
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Adding timing assumptions (I)
D
DTACK
LDS
map
csc
DSr
LDTACK
65
State space domain
DSr
LDTACK-
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State space domain
DSr
LDTACK-
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State space domain
DSr
LDTACK-
Two more unreachable states
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Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
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Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
One more DC vector for all signals
One state conflict is removed
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Netlist with one constraint
D
DTACK
LDS
map
csc
DSr
LDTACK
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Netlist with one constraint
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Timing assumptions

• (a before b) for concurrent events
  concurrency reduction for firing and
  enabling
• (a before b) for ordered events
  early enabling
• (a simultaneous to b wrt c) for triples of
  events combination of the above

73
Ordered events early enabling
b
b
a
c
c
F
G
a
b
c
74
Adding timing assumptions (II)
DSr
DTACK-
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
DSr
LDTACK
75
State space domain
LDS-
D-
DSr-
Reachable space is unchanged
For LDS- enabling can be changed in one state
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Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
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Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
-
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
One more DC vector for one signal LDS
If used LDS DSr, otherwise LDS DSr D
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Before early enabling
DSr
DTACK-
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
DSr
LDTACK
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Netlist with two constraints
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
DSr
LDS
LDTACK
Both timing assumptions are used for optimization
and become constraints
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Backannotation

• Timed circuits require post-verification
• Can synthesis tools help ?
• Report the least stringent set of timing
  assumptions required for the correctness of the
  circuit
• Not all initial timing assumptions may be
  required
• Petrify reports a set of firing order constraints
  that guarantee the circuit correctness

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Experiments

• Assumption delays are controllable in physical
  design
• 2-3x improvement in area/delay wrt to
  SI(K.Stevens, S.Rotem et al. Intel Corporation)
• Rotating Asynchronous Pentium Processor(TM)
• Instruction Decoder (Async99)

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Summary

• Synthesis of asynchronous circuits can be
  automated at gate level (logic synthesis)
• Timing assumptions/constraints are essential to
  compete with synchronous circuits
• Relative timing seems to be a promising approach
  for specification and synthesis
• High-level and logic synthesis can be
  combined(e.g. CSP ? Petri net ? circuit)

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Petrify

• The synthesis methodology presented in this
  tutorial is handled by petrify
• but also ...
• Concurrency reduction
• Automatic handshake expansion (2-4 phase)
• Noise isolation
• Synthesis with gC elements and gate libraries
• Synthesis of Petri nets (crucial for
  backannotation)
• ...

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Petrify implementation details

• 50,000 lines of code SIS (data structures
  logic synthesis) BDD package (symbolic
  manipulation) dot (graph visualization package
  from ATT)
• BDD-based implementation
• Reachability analysis
• Manipulation of sets of states
• Boolean minimization

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Petrify
http//www.lsi.upc.es/jordic/petrify

• References
• Tutorial for the designer
• Binaries (for several platforms)