ELEN 468 Advanced Logic Design

1
ELEN 468 Advanced Logic Design

• Lecture 10
• Behavioral Descriptions IV

2
Finite State Machines
Mealy Machine
input
output
Next state and output Combinational logic
Register
clock
Moore Machine
input
Next state Combinational logic
Output Combinational logic
output
Register
clock
3
Explicit Finite State Machines 1

• module FSM_style1 ( )
• input
• output
• parameter size
• reg size-10 state
• wire size-10 next_state // different from
  textbook
• // which is wrong
• assign outputs // function of state and
  inputs
• assign next_state // function of state and
  inputs
• always _at_ ( negedge reset or posedge clk )
• if ( reset 1b0 ) state start_state
• else state lt next_state
• endmodule

4
Explicit Finite State Machines 2

• module FSM_style2 ( )
• input
• output
• parameter size
• reg size-10 state, next_state
• assign outputs // function of state and
  inputs
• always _at_ ( state or inputs )
• begin
• // decode for next_state with case or if
  statement
• end
• always _at_ ( negedge reset or posedge clk )
• if ( reset 1b0 ) state start_state
• else state lt next_state
• endmodule

5
Explicit Finite State Machines 3

• module FSM_style3 ( )
• input
• output
• parameter size
• reg size-10 state, next_state
• always _at_ ( state or inputs )
• begin
• // decode for next_state with case or if
  statement
• end
• always _at_ ( negedge reset or posedge clk )
• if ( reset 1b0 ) state start_state
• else begin
• state lt next_state
• outputs lt some_value ( inputs, next_state )
• end
• endmodule

6
Summary of Explicit FSM

• States are defined explicitly
• FSM_style1
• Minimum behavioral description
• FSM_style2
• Use behavioral to define next state, easier to
  use
• FSM_style3
• Output synchronized with clock

7
FSM Example Speed Machine
8
Verilog Code for Speed Machine

• // Explicit FSM style
• module speed_machine ( clock, accelerator, brake,
  speed )
• input clock, accelerator, brake
• output 10 speed
• reg 10 state, next_state
• parameter stopped 2b00
• parameter s_slow 2b01
• parameter s_medium 2b10
• parameter s_high 2b11
• assign speed state
• always _at_ ( posedge clock )
• state lt next_state

• always _at_ ( state or accelerator or brake )
• if ( brake 1b1 )
• case ( state )
• stopped next_state lt stopped
• s_low next_state lt stopped
• s_medium next_state lt s_low
• s_high next_state lt s_medium
• default next_state lt stopped
• endcase
• else if ( accelerator 1b1 )
• case ( state )
• stopped next_state lt s_low
• s_low next_state lt s_medium
• s_medium next_state lt s_high
• s_high next_state lt s_high
• default next_state lt stopped
• endcase
• else next_state lt state
• endmodule

9
Implicit Finite State Machine

• module speed_machine2 ( clock, accelerator,
  brake, speed )
• input clock, accelerator, brake
• output 10 speed
• reg 10 speed
• define stopped 2b00
• define low 2b01
• define medium 2b10
• define high 2b11

• always _at_ ( posedge clock )
• if ( brake 1b1 )
• case ( speed )
• stopped speed lt stopped
• low speed lt stopped
• medium speed lt low
• high speed lt medium
• default speed lt stopped
• endcase
• else if ( accelerator 1b1 )
• case ( speed )
• stopped speed lt low
• low speed lt medium
• medium speed lt high
• high speed lt high
• default speed lt stopped
• endcase
• endmodule

10
Another Implicit FSM Example

• module speed_machine3 ( clock, accelerator,
  brake, speed )
• input clock, accelerator, brake
• output 10 speed
• reg 10 speed
• define stopped 2b00
• define low 2b01
• define medium 2b10
• define high 2b11

• always _at_ ( posedge clock )
• case ( speed )
• stopped if ( brake 1b1 )
• speed lt stopped
• else if ( accelerator 1b1 )
• speed lt low
• low if ( brake 1b1 )
• speed lt stopped
• else if ( accelerator 1b1 )
• speed lt medium
• medium if ( brake 1b1 )
• speed lt low
• else if ( accelerator 1b1 )
• speed lt high
• high if ( brake 1b1 )
• speed lt medium
• default speed lt stopped
• endcase
• endmodule

11
Handshaking
Server
Client
8
data_out
data_in
server_ready
server_ready
client_ready
client_ready
12
Algorithm State Machine (ASM) Chart
c_idle / CR 0
s_idle / SR 0


s_wait / SR 1
c_wait / CR 1
0
0
1
1


s_serve / SR 1
c_client / CR 1


s_done / SR 0
c_done / CR 0


0
1
0
1
13
Verilog Code for Handshaking

• module server ( d_out, s_ready, c_ready )
• output 30 d_out output s_ready
• input c_ready
• reg s_ready reg 30 d_out
• task pause
• reg 30 delay
• begin delay random
• if ( delay 0 ) delay 1
• delay end
• endtask
• always
• forever begin
• s_ready 0 pause s_ready 1
• wait ( c_ready ) pause
• d_out random pause
• s_ready 0
• wait ( !c_ready ) pause
• end
• endmodule

• module client ( d_in, s_ready, c_ready )
• input 30 d_in input s_ready
• output c_ready
• reg c_ready reg 30 data_reg
• task pause
• reg 30 delay
• begin delay random
• if ( delay 0 ) delay 1
• delay end
• endtask
• always begin
• c_ready 0 pause c_ready 1
• forever begin
• wait ( s_ready ) pause
• data_reg d_in pause c_ready 0
• wait ( !s_ready ) pause c_ready 1
• end
• end
• endmodule

14
Polling Circuit
Each client cannot be served for 2 consecutive
cycles
client1
service request
clock
3
Polling circuit
Server
client2
2
reset
service code
client3
Highest priority
15
State Transition Graph for Polling Circuit
100
Client3 11
Service request
-01
-1-
1--
000
1--
1--
010
001
000
000
None 00
Client2 10
Client1 01
01-
001
000
0-1
Service code
01-
16
Verilog Code for Polling Circuit

• module polling ( s_request, s_code, clk, rst )
• define client1 2b01
• define client2 2b10
• define client3 2b11
• define none 2b00
• input 31 s_request
• input clk, rst output 10 s_code
• reg 10 next_client, present_client
• always _at_ ( posedge clk or posedge rst )
• begin if ( rst )
• present_client none
• else present_client next_client
• end
• assign s_code10 present_client
• always _at_ ( present_client or s_request )
• begin
• poll_them ( present_client,
  s_request,
• next_client )
• end

• task poll_them
• input 10 present_client
• input 31 s_request
• output 10 next_client
• reg 10 contender integer N
• begin poll
• contender none
• next_client none
• for ( N 3 N gt 1 N N 1 )
• begin decision
• if ( s_requestN ) begin
• if ( present_client N
  )
• contender
  present_client
• else begin next_client N
• disable poll end
• end end
• if (( next_client none )
• ( contender ))
• next_client contender end

17
Test Bench for Polling Circuit

• moduel test_polling
• reg 31 s_request reg clk, rst
• wire 10 s_code
• wire sreq3 M1.s_request3
• wire sreq2 M1.s_request2
• wire sreq1 M1.s_request1
• wire 10 NC M1.next_client
• wire 10 PC M1.present_client
• wire 31 s_req s_request
• wire 10 s_cd s_code
• polling M1 ( s_request, s_code, clk, rst )
• initial begin
• clk 0 forever 10 clk clk
• end
• initial 400 finish
• initial begin
• rst 1bx
• 25 rst 1 75 rst 0
• end

• initial
• begin
• 20 s_request 3b100
• 20 s_request 3b010
• 20 s_request 3b001
• 20 s_request 3b100
• 40 s_request 3b010
• 40 s_request 3b001
• end
• initial
• begin
• 180 s_request 3b111
• 60 s_request 3b101
• 60 s_request 3b011
• 60 s_request 3b111
• 20 rst 1
• end
• endmodule

18
Exercise 2
19
Find Error

• module something_wrong ( y_out, x1, x2 )
• output y_out
• input x1, x2
• define delay1 3 // No
• define delay2 4
• define delay3 5
• nand (delay1, delay2, delay3) ( y_out, x1, x2
  )
• // No turnoff delay for non-3-state gate
• // Remove delay3, or replace , with
• endmodule

20
Timing Models

• Determine time values in simulation
• timescale 10ns/1ps 2.447 24.470ns
• timescale 1ns/100ps 2.447 2.4ns
• What is the typical falling delay from a1 to y2?
• (a1,a2 gt y1, y2) (789, 61012)
• 10

21
Correct Error

• module flop ( clock, data, q, qbar, reset )
• input clock, data, reset
• output q, qbar
• reg q
• assign qbar q
• // This cannot model flip-flop properly
• // when reset rises and clock 1
• always _at_ ( posedge clock or reset )
• begin
• if ( reset 0 ) q 0
• else if ( clock 1 ) q data
• end
• endmodule

22
What will happen?

• module A ( )
• initial
• clock 0
• // Nothing will happen
• always _at_ ( clock )
• clock clock
• endmodule