ELEN 468 Advanced Logic Design

1
ELEN 468Advanced Logic Design

• Lecture 24
• Design for Testability

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Test Cost

• Test pattern generation
• Fault simulation
• Generation of fault sites information
• Test equipment
• Test process
• Test cost may overweight design cost

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Why Design for Testability?

• Testability is a design characteristic that
  influences various costs associated with testing
• It allows for
• Device status to be determined
• Isolation of faults
• Reduce test time and cost

4
Controllability

• Ability to establish a specific signal value at
  each node by setting circuits inputs
• Circuits typically difficult to control
  decoders, circuits with feedback, oscillators,
  clock generators

5
Observability

• Ability to determine the signal value at any node
  in a circuit by controlling the circuits inputs
  and observing its output

6
Predictability

• Ability to obtain known output values in response
  to given input stimuli
• Factors affecting predictability
• Initial state of circuit
• Races
• Hazards

7
Difficult Test Cases

• Sequential logic is more difficult to test than
  combinational logic
• Control logic is more difficult to test than
  data-path logic
• Random logic is more difficult to test than
  structured bus-oriented designs
• Asynchronous design is more difficult to test
  than synchronous design

8
Quantify Testability

• Need approximate measure of
• Difficulty of setting internal circuit lines to 0
  or 1 by setting primary circuit inputs
• Difficulty of observing internal circuit lines by
  observing primary outputs
• Uses
• Analysis of difficulty of testing internal
  circuit parts redesign or add special test
  hardware
• Guidance for algorithms computing test patterns
  avoid using hard-to-control lines
• Estimation of fault coverage
• Estimation of test vector length

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Types of Measures

• SCOAP Sandia Controllability and Observability
  Analysis Program
• Combinational measures
• CC0 Difficulty of setting circuit line to logic
  0
• CC1 Difficulty of setting circuit line to logic
  1
• CO Difficulty of observing a circuit line
• Sequential measures analogous
• SC0
• SC1
• SO

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Range of SCOAP Measures

• Controllabilities 1 (easiest) to infinity
  (hardest)
• Observabilities 0 (easiest) to infinity
  (hardest)
• Combinational measures
• Roughly proportional to circuit lines that must
  be set to control or observe given line
• Sequential measures
• Roughly proportional to times a flip-flop must
  be clocked to control or observe given line

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Controllability Examples
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Observability Examples
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Goal of Design for Testability (DFT)

• Improve
• Controllability
• Observability
• Predictability

14
Design and Test Trade-off

• Most DFT ( Design for Testability ) techniques
  need extra hardware, or modification to circuits
  that may affect performances
• DFT need to consider the cost trade-off between
  design and test

15
DFT Methods

• DFT methods for digital circuits
• Ad-hoc methods
• Structured methods
• Scan
• Partial Scan
• Built-in self-test (BIST)
• Boundary scan

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Ad-Hoc DFT Methods

• Good design practices learnt through experience
  are used as guidelines
• Avoid asynchronous (unclocked) feedback
• Make flip-flops initializable
• Avoid redundant gates
• Avoid large fanin gates
• Provide test control for difficult-to-control
  signals
• Avoid gated clocks
• Design reviews conducted by experts or design
  auditing tools
• Disadvantages of ad-hoc DFT methods
• Experts and tools not always available
• Test generation is often manual with no guarantee
  of high fault coverage
• Design iterations may be necessary

17
Scan Design

• Circuit is designed using pre-specified design
  rules
• Test structure (hardware) is added to the
  verified design
• Add a test control (TC) primary input
• Replace flip-flops by scan flip-flops (SFF) and
  connect to form one or more shift registers in
  the test mode
• Make input/output of each scan shift register
  controllable/observable from PI/PO

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Scan Design Rules

• Use only clocked D-type of flip-flops for all
  state variables
• At least one PI pin must be available for test
  more pins, if available, can be used
• All clocks must be controlled from PIs

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Correcting a Rule Violation

• All clocks must be controlled from PIs

Comb. logic
D1
Q
Comb. logic
FF
D2
CK
Comb. logic
Q
D1
Comb. logic
FF
D2
CK
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Scan Storage Cell
Q, So
D
Si
SSC
N/T
SSC
Clk
Q
D
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Scan Flip-Flop (SFF)
Master latch
Slave latch
D
N/T
Q
Logic overhead
MUX
Q
Si
Clk
D flip-flop
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Scan Methods
C1
C2
C2
C1
MUX
Si
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Boundary Scan
MUX
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Integrated Serial Scan
PI
PO
SFF
SCANOUT
Combinational logic
SFF
SFF
Control
SCANIN