CS 2200 Lecture 07a MIPS control review, microcoding, execeptions

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CS 2200 Lecture 07a MIPS control review,
microcoding, execeptions

• (Lectures based on the work of Jay Brockman,
  Sharon Hu, Randy Katz, Peter Kogge, Bill Leahy,
  Ken MacKenzie, Richard Murphy, and Michael
  Niemier)

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Control logic for a single cycle machine
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Implementation Overview
simplest view of Von Neumann, RISC mP

• Abstract / Simplified View
• Two types of signals data and control
• clocking strategy
• All storage elements are clocked by the same
  clock edge.

Data
Address
PC
Ra
Instruction
Address
Rb
A
L
U
Instruction Memory
Register File
Rw
Data Memory
Data
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MIPS instruction formats

• R-type format (i.e. ADD, SUB, OR, etc.)
• I-type format (i.e. ADDI, LW, SW, BEQ)
• J-type (i.e. JUMP)

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The HW needed, plus control
Single cycle MIPS machine
When we talk about control, we talk about these
blocks
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Implementing Control

• Implementation Steps Review
• Identify control inputs and control outputs
• Make a control signal table for each cycle
• Derive control logic from the control table
• As youve seen (and as well review), this logic
  can take on many forms combinational logic,
  ROMs, microcode, or combinations

I promise. This is not a hard thing to do. Dont
be intimated by complex datapath.
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Single Cycle Control Input/Output

• Control Inputs
• Opcode (6 bits)
• How about R-type instructions?
• Control Outputs
• RegDst
• ALUSrc
• MemtoReg
• RegWrite
• MemRead
• MemWrite
• Branch
• Jump
• ALUctr

Step 2 Make a control signal table for each cycle
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Control Signal Table
(inputs)
R-type
(outputs)
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The HW needed, plus control
Single cycle MIPS machine
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Main control, ALU control
Func
ALUctr
OP
ALU Control
Main Control
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ALUOp
3
6
2
(opcode)
ALU
Other cnt. signals

• Use OP field to generate ALUOp (encoding)
• Control signal fed to ALU control block
• Use Func field and ALUOp to generate ALUctr
  (decoding)
• Specifically sets 3 ALU control signals
• B-Invert, Carry-in, operation

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Main control, ALU control
Or in other words 00 ALU performs add 01 ALU
performs sub 10 ALU does what function code
says (see p. 284 for more)
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Generating ALUctr

• We want these outputs

and - 00
or - 01
mux
adder - 10
ALUctrlt2gt B-negate (C-in B-invert) ALUctrlt1gt
Select ALU Output ALUctrlt0gt Select ALU Output
Invert B and C-in must be a 1 for subtract
less - 11
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The Logic
This table is used to generate the actual Boolean
logic gates that produce ALUctr.
Could generate gates by hand, often done w/SW.
(ALUOp)
ALUOp0
X/1
ALUctrlt2gt
ALUOp1
1/0
0/X
1/1
F3
1/0
ALUctr
(funclt50gt)
110/110
ALUctrlt1gt
F2
0/X
1/1
Ex ALUctrlt2gt (SUB/BEQ)
ALUctrlt0gt
F1
1/X
0/0
0/0
F0
0/X
0/X
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Recall
Single cycle MIPS machine
Recall, for MIPS, we have to build a Main Control
Block and an ALU Control Block
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Well, heres what we did
Single cycle MIPS machine
We came up with the information to generate this
logic which would fit here in the datapath.
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Single cycle versus multi-cycle
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Single cycle
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Multi-cycle
(Now, critical path dependent on longest
delay for string of components used in 1 of 5
steps)

• Where do we need to insert muxs?
• Other functional units?

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Execution Sequence Summary
IR ? MemoryPC
PC ? PC 4
A ? RegIR(2521)
B ? RegIR(2016)
ALUOut ? PC SignEx(IR(150) ltlt 2)
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Multiple Cycle Design

• Break up the instructions into steps, each step
  takes a cycle
• balance the amount of work to be done
• restrict each cycle to use only one major
  functional unit
• At the end of a cycle
• store values for use in later cycles (easiest
  thing to do)
• introduce additional internal registers

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Control Signals
New
Old

• PC PCWrite, PCWriteCond, PCSource
• Memory IorD, MemRead, MemWrite
• IR IRWrite
• Reg. File RegWrite, MemtoReg, RegDst
• ALU ALUSrcA, ALUSrcB, ALUOp, ALUCnt.

RegDst, MemToReg, RegWrite, MemRead, MemWrite,
Branch, ALUSrc, ALUOp, ALUCnt.
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Implementing the Control

• Value of control signals is dependent upon
• what instruction is being executed
• which step is being performed
• Use the information weve acculumated to specify
  a finite state machine
• use a state diagram, or
• use microprogramming
• Implementation can be derived from specification

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Graphical Specification of FSM
t
Instruction Fetch
MemRead ALUSrcA 0 IorD 0 IRWrite ALUSrcB
01 ALUOp 00 PCWrite PCSource 00
Instruction decode/ Register fetch
1
0
ALUSrcA 0 ALUSrcB 11 ALUOp 00
start
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9
Branch Completion
Memory address computation
Jump Completion
2
6
Execution
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond PCSource 01
ALUSrcA 1 ALUSrcB 10 ALUOp 00
ALUSrcA 1 ALUSrcB 00 ALUOp 10
PCWrite PCSource 10
Memory access
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Memory access
RegDst 1 RegWrite MemToReg 0
MemRead IorD 1
MemRead IorD 1
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Tells us what values are needed and during what
step
R-type completion
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RegDst 0 RegWrite MemToReg 1
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Memory read completion
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Finite State Machine for Control
Control logic is inside this box (could be
implemented in many different ways)
The outputs that we want now also dependent
on the current state.
could be ROM, logic, etc.
Inputs (which now also include the previous state)
(Still might need ALU control logic and hence
function code developed earlier)
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Microprogramming

• For what weve been doing, state diagrams and
  combinational logic have been more than adequate
• But remember, were dealing with only a small
  subset of the MIPS processor
• Full MIPS instruction set has over 100
  instructions
• Also, in 1 implementation instructions take from
  1 clock cycle to 20 clock cycles
• Clearly, control would be much more complex for
  this case
• Another alternativemicrocoding
• Think of control signals that must be asserted in
  a state as an instruction to be executed by the
  datapath
• Call these micro instructions

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Micro-instructions

• Microinstruction
• A set of datapath control signals that must be
  asserted in a given state
• Executing has affect of asserting control signals
  specified by the instruction
• How do we sequence?
• In some cases, just fetch the next instruction
• Next instruction just depends on the state
• In others, need to consider inputs
• i.e. next instruction depends on the state and
  the input
• Like assembly language, must branch explicitly
• Designing control as a program that implements
  the machine instructions in simpler terms is
  microprogramming

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Microprogramming guidelines

• Make each field of microinstruction responsible
  for specifying a non-overlapping set of control
  signals
• Signals that are never asserted simultaneously
  may share the same field
• Have signals that control datapath elements and a
  field that handles sequencing
• (i.e. selecting the next instruction)
• Microinstructions usually in a ROM or PLA
• Therefore can assign addresses
• Like choosing s for FSM elements

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Example fields
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Choosing the next instruction

• How to we choose whats next?
• Increment the address of the current
  microinstruction to obtain the next
• Put Seq in the sequencing field
• (Most common case, usually default)
• Branch to the next microinstruction
• Place Fetch in the sequencing field
• Choose next microinstruction based on control
  unit inputs
• This is called a dispatch
• Usually implemented by creating a table
  containing addresses of target microinstructions
• (May be implemented in a ROM)

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Dispatch tables

• Often, (and realistically), there is more than 1
• Example state diagram constructed earlier
• We would need 2 dispatch tables here
• 1 to dispatch from state 1
• 1 to dispatch from state 2
• Indicate the next microinstruction should be
  chosen by a dispatch operation by placing
  dispatch i in the sequencing field
• (i is table )

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Possible Values
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Creating the microprogram

• In writing a microprogram, there are two
  situations in which we may want to leave a field
  of the microinstruction blank
• When a field that controls a functional unit or
  that causes state to be written
• (i.e. the Memory field or the ALU dest field) is
  blank, no control signals should be asserted
• When a field only specifies the control of a
  multiplexor that determines the input to a
  functional unit, such as the SRC1 field
• leaving it blank means that we do not care
  about the input to the functional unit (or the
  output of the multiplexor)

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Example

• The 1st component of every instruction execution
  is to fetch the instructions, decode them, and
  compute both the sequential PC and branch target
  PC
• Correspond directly to the 1st 2 steps of
  execution described (see pages 385-388)
• The 2 microinstructions needed for these 1st two
  steps are shown below

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Example

• To understand what each microinstruction does, it
  is easiest to look at the effect of a group of
  fields
• In the first microinstructions, the fields
  asserted and their effects are as follows

The label field, containing the label Fetch, will
be used in the Sequencing field when the
microprogram wants to start the execution of the
next instruction.
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The entire microprogram
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Control Example

• Can you generate the control signal table?
• How about micro-programmed implementation?

i
l
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Sample Microinstruction

• Ifetch IR lt- MemPC PC lt- PC4

Microinstruction 1d011ddd000100d11
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A few words on MIPS exceptions
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What is an exception?

• Exception
• An event other than a branch or a jump that
  changes the normal flow of an instruction
  execution
• Often called an interrupt as well
• Examples

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Processing exceptions

• For the OS to process an exception, it must know
  why it was caused and which instruction cause it
• (i.e. arithmetic exception, invalid instruction)
• One method
• (used in MIPS)
• Have a status register called the Cause Register
• Holds a field that indicates the reason for the
  exception
• Another method
• Vectored interrupts
• Address to which control is transferred is
  determined by cause of the exception
• OS knows the reason for the exception by the
  address at which its initiated

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Need more HW

• To process exceptions we need more HW
• EPC
• A 32-bit register that holds address of affected
  instruction
• (Needed even with vectored interrupts)
• Cause
• A register used to record the cause of the
  exception
• In MIPS, 32 bits
• Well also need 2 more control signals
• EPCWrite and CauseWrite

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Finally, augmenting our FSM
t
Instruction Fetch
MemRead ALUSrcA 0 IorD 0 IRWrite ALUSrcB
01 ALUOp 00 PCWrite PCSource 00
Instruction decode/ Register fetch
1
0
ALUSrcA 0 ALUSrcB 11 ALUOp 00
start
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Branch Completion
Jump Completion
Memory address computation
2
6
Execution
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond PCSource 01
PCWrite PCSource 10
ALUSrcA 1 ALUSrcB 10 ALUOp 00
ALUSrcA 1 ALUSrcB 00 ALUOp 10
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Op other
Memory access
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IntCause 1 CauseWrite ALUSrcA 0 ALUSrcB
01 ALUOp 01 EPCWrite PCWrite PCSource 11
IntCause 0 CauseWrite ALUSrcA 0 ALUSrcB
01 ALUOp 01 EPCWrite PCWrite PCSource 11
Memory access
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RegDst 1 RegWrite MemToReg 0
Overflow
MemRead IorD 1
MemRead IorD 1
3
R-type completion
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RegDst 0 RegWrite MemToReg 1
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Memory read completion