Diapositive 1

1
Challenges for the ATLAS Upgrade Tracker at SLHC
Didier Ferrère, DPNC Université de Genève
In behalf of the ATLAS Upgrade community
4th Trento Workshop
2
Motivations
Increase the luminosity at SLHC by a factor of
10 and the proton energy of up to 12.5TeV by
considering upgrade of the machine and
consequently of the experiments
The future observations at LHC should drive
physics investigations at SLHC
4th Trento Workshop, D. Ferrère
2
3
Machine Scenario
4th Trento Workshop, D. Ferrère
3
4
B-Layer Replacement

• Current B-Layer may not survive until end of
  phase I 2012 (Radiation damage Inefficiencies
  at high rate).
• BL Task Force was led last year by (A. Clark, G.
  Monarcchi).
• ? Conclusion was given end of 2008
• ? Proposal for an Insertable B-Layer (IBL)
  inside the current pixel detector
• Many challenges, both technical and time scale
  to be ready for integration to beam-pipe.
• A number of critical issues will possibly
  requiring reviews in 2009
• ? Mechanics and removal/installation scenario
• ? Cooling
• ? Sensor technology
• ? Readout
• ? Technical proposal

Schedule - 2009 WBS, Cost, schedule by Apr 09
and TP to be reviewed Jun 09 - 2010 TDR - 2011
Production - 2012 Installation
4th Trento Workshop, D. Ferrère
4
5
IBL development
Current pixel module with FE-I3 ? Single chip
pixel modules on stave
4th Trento Workshop, D. Ferrère
5
6
Detector Upgrade Plan

• Current ID is design to survive 600fb-1
  integrated luminosity expected for 2016
• New ID is therefore planned for
  installation/operation in 2018 with a higher
  yearly integrated luminosity of 600fb-1
• Many challenges and critical issues Under
  investigation for most of them
• Schedule
• - End of 2009 Letter Of Intend
• - 2010 Technical Proposal
• - 2011 Costing and MOU by April and TDR by
  December
• - 2012 PRRs
• - 2017 Installation at the end of the year
• Upgrade organization Executive bodies, Steering
  Group, Technical Coordination, Project Office and
  Working groups

The Upgrade community has to keep in mind the
detector challenges at SLHC
4th Trento Workshop, D. Ferrère
6
7
DCS
Layout
Trigger
Tracking Performance
4th Trento Workshop, D. Ferrère
7
8
ID Upgrade Issues
Topics under investigation for the tracker
upgrade

• New ID layout Only silicon pixel and strip
  detectors ? Simulations
• Trigger Si-track trigger for L1 inside ID is
  desirable
• New detector technology n-in-p planar for
  strips and pixel outers, 3D-sensors (B-Layer),
  Diamond (B-Layer)
• New ASICs technologies Deep submicron 250 nm
  ?130nm or 90 nm
• Cooling with more headroom Silicon temperature
  below -20C
• New powering scheme Serial powering or DC-DC
  for parallel powering
• Faster readout FE asics (160/320 Mbps) and
  optical link (5Gb/s)
• SCT 1.3 kch/link ? Upgrade 123 kch/link
• Module integration will be grouped on a stave or
  a super-module structure ? performances
• DCS is proposed to be partially integrated into
  the readout architecture
• Engineering
• - Assemble and commission the complete ID in a
  surface building
• - Service reuse of cables between counting room
  and detector
• Installation Limited access time inside the
  cavern

4th Trento Workshop, D. Ferrère
8
9
Silicon in the ID Today
SCT EC at SR1
63 m2 of silicon installed today ? more than 10
years of RD, production, integration and
installation
SCT barrel integration
9
10
ID Upgrade Layout
Including disks this leads to Pixels 5 m2,
300,000,000 channels Short strips 60 m2,
30,000,000 channels Long strips 100 m2,
15,000,000 channels
Evolution of Strawman Layout since 2006 ? Fixed
length barrel Stawman08
2 layers - 3 layers - 4 layers -
Strawman06
4th Trento Workshop, D. Ferrère
10
11
Sensor Technology
Pixel b-layer 3D technology option Ready for
2012 IBL?
Pixel and Strips n-in-p (planar technology)
Exist in single and double column type

• No type inversion, full depletion is on
  structured side
• Collection of electrons (faster than p-in-n)
• Reverse annealing is contained

ionizing particle
n-columns
Still 10-12 ke- at 1.1015 cm-2s-1 (FZ or MCZ)

• Strip of 2.5cm long and ABCN 250nm
• _at_500V we expect 750e- Ileak0.9mA _at_ -15C
• S/N of 12-15

p-Si
Topics covered by the Workshop
Pixel b-layer Diamond option
Option for b-layer at sLHC
Good points Low noise, small Ileak, no runaway
pCVD
electrons swept away by transversal field
holes drift in central region and diffuse towards
p contact
4th Trento Workshop, D. Ferrère
11
12
Module Integration

• Critical issues
• Contain the material budget with design and
  technology optimization
• Tracker need precision built-in accuracy and
  mechanical stability
• Thermal management is critical to prevent
  runaway on the silicon
• ? cooling, design, material and performance to
  be optimized
• Manufacturability, yield and cost
• Need to prove in case of strip stave that
  performances are not affected by the hybrid
  gluing on top of the Si-surface
• Bare Pixel module Single or multi-chip design
• Integration or new technology (3D, Diamond, )
  need more RD

Pixel Module stave cross section
4th Trento Workshop, D. Ferrère
12
13
Module Integration
Pixel outer layer baseline
4-chip module using 80 col x 336 row FE-I4 chip
Carl Haber LBNL
Prototype with ABCD chip
1.2m
4 rows of 2.5cm strip/Si wafer (1280 ch/row)
Short Strip Stave Baseline
4th Trento Workshop, D. Ferrère
13
14
Double-sided Strip Modules - Backup
Lateral insertion (KEK)

• End insertion (Geneva)

4th Trento Workshop, D. Ferrère
14
15
Strip Endcap Module Integration
Possible powering scheme

• Endcap strip
• 5 discs on each side
• 32 petals/disc
• ? 4 different petals (325mmltRlt950mm)
• 6 different detector types mounted on petals
• ? Max 18 sensors/petal
• ? Min. 12 sensors/ petal
• ? Issues Layout, modularity, powering

C. Lacasta IFIC
DC-DC
Serial
Dc-dc eff 60-75 Disc power 1230 W
2 cables - eff 55-65 Disc power 1440 W
4th Trento Workshop, D. Ferrère
15
16
Module Integration - Thermal
Tmax (FE) -19.4C
Cooling _at_ -30C with CO2
Tmax (Si) -20.7C
Short-Strip Stave with convection and radiation in
sLHC
Uncontrolled Tgas has a significant impact on
Si-temperature and on the runaway!
4th Trento Workshop, D. Ferrère
16
17
New Readout Electronics

• CMOS (250nm, 130nm or 90nm) is the technology
  choice for the Upgrade
• Known for the radiation hardness
• Good for large volume production
• Promising for low power consumption

Pixel FE-I3 (250nm) ? FE-I4 (130nm) Strip ABCN
250nm ? 130nm
_at_ 320 MHz _at_ 160 MHz
Current Asics program

• Issues
• Technology choice for a production in gt 3 years
  250nm, 130nm, 90nm?
• Power consumption (Strips)
• - 250nm ? Measured 3.6 mW/ch _at_ 40MHz
• - 130nm ? Estimated 1 mW/ch _at_ 160MHz
• Single Event Upset (SEU)
• 130 nm technology seems to be 10 times more
  sensitive than 250 nm
• New readout protocol has to be considered (avoid
  Token, data coding)
• Design ? prototype and tests ? manufacturability
  on a fixed timescale
• Design and tools of 130nm or 90nm looks more
  complex

4th Trento Workshop, D. Ferrère
17
18
Strip ABCN chips
Digital part reuse of existing SCT protocols,
SEU protections, 80Mbits/sec output rate, power
control , 2mW/channel _at_2.5V
128 Channels Front-End opt. for Short
Strips 0.7mW/channel
ABCN 250nm is an intermediate version of the FE
chip for modules prototypes developments
F. Anghinolfi
Serial regulator to provide analogue from a
unique digital analogue power source
Shunt regulators (2 options) to exercise 2
different serial powering systems
4th Trento Workshop, D. Ferrère
18
19
Strip ABCN chips

• ABCN program
• Test and validate the current chips in 250nm
  technology
• Use those chips for prototypes
• Work on the final choice technology

A. Greenall

• Good progress so far in testing
• - Digital and analog performance as expected
• - No malfunctioning found
• - Yield seems good
• Functionality and performances to be tested
  _at_80MHz
• Wafer screening under investigation

Noise as expected 380e
4th Trento Workshop, D. Ferrère
19
20
Data Transmission
Work focus on high speed data link _at_ 5Gbps to
minimize the number of fibers
The data transmission will be done for a complete
stave (Pixel) or half stave (Strip)
5 Gbps
10 Gbps

• Challenges and investigations
• Opto-devices not enough radiation hard for the
  pixel region ? need several meters of copper
  traces for the 5 Gbps link between GBT and Opto
• Radiation harness of all the components
• Bit Error Rate (BER) versus SEU ? Burst error
  correction scheme
• Wavelength study 850nm versus 1310 nm (more
  radiation hard)
• Versatile link working group well structure

4th Trento Workshop, D. Ferrère
20
21
Powering
ID Upgrade has a lot of more channels to power
than current ID
2 options are considered - Serial powering
- DC-DC conversion
ABC-Next 250 nm Vcc 2.2 V, Icc 0.036
A Vdd 2.5 V, Idd 0.12 A 0.38W/FE ?
30.4W/module ? 365W/stave
IP
ABC-Next 130 nm 1mW/ch expected 0.13W/FE ?
10.2W/module ? 123W/stave
SP
IP ? 2 order of magnitude higher of line width
than SP or DC-DC
DC-DC

• Issues
• DC-DC EMI (switching noise) radiation-hardness
  high gain/efficiency
• Serial Powering Optimize protection/by-pass
  circuitry Evaluate custom circuitry and identify
  best architecture
• System Work out cable budget b-layer upgrade
  power base line schedule

4th Trento Workshop, D. Ferrère
21
22
Serial Powering - System test
4 V x 30 hybrids 120 V (0.8 A)
Strip Stave from LBNL
In future 1.5V X 20 hybrids 30 V
4th Trento Workshop, D. Ferrère
22
23
DC- DC Powering Scheme
Key features Efficiency, modularity, flexibility
Work development common at CERN for ATLAS and CMS
Voltage for SMC and optoelectronics generated
locally by a converter stage 1
Stave
Only 1 power line/stave 10-12V

• Distribution with 2 conversion stages
• Stage 1
• 2 converters 2.5V analog and 1.8V digital
• Higher efficiency if more hybrid powered
• Integrated into a modular circuit board
• Stage 2
• Directly integrated into the FE asics
• Switched capacitor converter with fixed
  conversion ratio 2
• 2 converters one for analog and one for digital

4th Trento Workshop, D. Ferrère
23
24
Cooling
One of the keys in the operational success!

• Issues
• Define the fluid coolant CO2 versus C3F8
• Service reuse and segmentation
• Manifolding and impact on the system
• Module design is directly dependent of the
  cooling choice
• Requirements and specifications to be well
  defined and written-up

• Known
• C3F8 We learnt a lot and still may be a lot to
  learn in long term operation!
• ? Already a plant running BUT would it still be
  satisfactory in 10 years
• ? Need to improve the pressure drop in the
  exhaust to allow a temperature close to -30C.
• CO2 LHCb, AMS have it! Looks good but not
  easily scalable to ID Upgrade but fine for IBL!
• ? Less material for pipes, fittings and
  manifolds inside the ID volume
• ? More safety margin for Si temperature.

4th Trento Workshop, D. Ferrère
24
25
CO2 Cooling

• Need cooling facilities ? two different ways to
  test CO2 system in lab
• Blown system with exhaust lost Cheap but
  limited in control
• Close loop either with compressor or pump
  Expensive but controllable

Cooling tests at SLAC, M. Oriunno
Blown CO2 system
4th Trento Workshop, D. Ferrère
25
26
CO2 Cooling
As in CO2 refrigeration industry
Subritical vapor-compression cycle
Liquid
Vapor
Compressor
Hex
Gas return
Pressure
2-phase
Warm transfer
Chiller
Liquid supply
Enthalpy
Detector
Cooling plant
LHCb-VELO

• 2PACL pumped liquid system
• Fluid CO2

Liquid
Vapor
Pump
Pressure
2-phase
Chiller
Liquid circulation
Cold transfer
Enthalpy
Enthalpy
Detector
Cooling plant
4th Trento Workshop, D. Ferrère
26
27
Detector Control System
Motivation Define the DCS as early as possible
such it is integrated into the readout
architecture together with the powering and the
services.
DCS for diagnostics
DCS chain could be considered already at the chip
level!
DCS on SPI/LVDS from/to other SMC (Option 2)
DCS desired rate 1Hz
DCS for module interlock Module temp
ABCn
Data/DCS
MCC_1
Data/DCS stream 1
SMC
Data/DCS stream (Option 1/3)

DCS
DCS
GBT
Data/DCS stream 2
ABCn
Data/DCS
MCC_2
Data/DCS stream 24

• Direct DCS
• Interlock
• Environmental

DCS
5 Gbps
160-320 Mbps
4th Trento Workshop, D. Ferrère
27
28
Integration
Baseline - Integration of a 7 m long ID on the
surface - Room for insertable/removable b-layer

• Issues
• Layout not defined yet ? Engineering is based on
  1 layout (not optimized)
• Analysis (FEM) and dimensioning of main
  structural elements
• Critical points under investigation

• Service space inside the ID volume critical
  between EC and Barrel strips and in the flange
  region
• End of barrel strip where SMC and dense service
  region is expected
• Cooling distribution and manifolds
• Thermal management OC and Poly-moderator
• Pixel optoboards position
• PPF1 connection area and arrangement

4th Trento Workshop, D. Ferrère
28
29
Integration
F. Cadoux Uni. Genève
UM0.08mm
Very preliminary FEA calculation! EC
poly-moderator parts to be included for the
structural deformation vs temperature
Pixel load included with safety factor
4th Trento Workshop, D. Ferrère
29
30
Services
It is where there is a lot of constrains!

• Constrains
• Low mass inside the ID volume required
• Connection to the ID flanges should be fast and
  reliable
• Have to deal with the existing cables from
  counting rooms to PP2
• It has been excluded to reuse all the services
  at the various PP1 position
• For cooling pipes the cooling choice will
  strongly define what to do and the possible
  recycling
• Limited access due to radioactivity level (next
  slide)

4th Trento Workshop, D. Ferrère
30
31
Radiation Level
IssueRequirements to reuse much of ATLAS and
the levels of activation anticipated ? greatly
complicate installation
? Minimize the tasks
?1 week for catA (lt6mSv/y) ? 2.5 weeks for catB
(lt15mSv/y)
4th Trento Workshop, D. Ferrère
31
32
Conclusions

• ATLAS Upgrade at sLHC not approved yet but
  organizational structure already in place to
  steer the development, RD and the engineering
  efforts
• LOI is targeted this year towards the TP, TDR,
  production and Installation
• Schedule is based on the assumption that the
  Upgrade detector is installed and operational in
  2018
• The ATLAS ID will be completely renewed with
  165m2 of Silicon sensors
• The challenges are important Layout definition,
  service and material reductions, readout
  architecture, cooling, powering scheme, schedule,
  
• Significant efforts in working groups started to
  tackle these new challenges
• The evaluation of prototypes functionality will
  be a major step in the near future
• Next events
• Atlas Upgrade week (twice a year) 23-27
  February at CERN
• ACES09 ATLAS-CMS workshop on electronics for
  the SLHC 3-4 March at CERN

4th Trento Workshop, D. Ferrère
32
33
Back-up Slides
Back-up Slides
4th Trento Workshop, D. Ferrère
33
34
Beam
nominal
25 ns
new alternative!
ultimate 25-ns upgrade
25 ns
50-ns upgrade, no collisions _at_S-LHCb!
50 ns
new baseline!
50-ns upgrade with 25-ns collisions in LHCb
50 ns
25 ns
4th Trento Workshop, D. Ferrère
34
35
Beam
4th Trento Workshop, D. Ferrère
35
36
Strip Readout Architecture
Next time, lets not just get hung up over
material at ?0. This is supposed to be a tracker
up to ?2.5
4th Trento Workshop, D. Ferrère
36
37
Strip Readout Architecture
FE Chip
FEIC
x10-20 /MC
TTC
N Links
Data
Module
Controller
TTC
Electrical LVDS
Electrical LVDS
Data
MC
x24 /SC
M Links
Stave
Optical links
TTC
Controller

• Difference with current SCT architecture
• MC and SC stages
• FE Data at 160-320 instead of 40 Mbps
• Data to off-detector will transit via high speed
  links 5Gbps
• Top and bottom side readout are decoupled
• DCS diagnostics data possibly integrated into
  the readout chain
• FE redundancy scheme is differently implemented
  (No bypass)
• Readout protocol has to be different (avoid
  token, data coding,)

Data
SC
x2 /stave
4th Trento Workshop, D. Ferrère
37
38
Strip Readout Architecture
Absolute requirement is to prevent the readout
chain against off-state due to SEU
? Smooth run operation

• 130 nm technology has higher cross-section SEU
  due to smaller geometry and smaller digital
  voltage
• Need to implement replica logic (triple vote
  logic) to increase SEU tolerances
• Replica logics consume 3 times more space and
  therefore has to be used where it is absolutely
  necessary
• P-I-N diodes and BER versus SEU has been studied
  by Versatile link teams

Measurements obtained with a test system at PSI
4th Trento Workshop, D. Ferrère
38
39
Cooling
A very preliminar proposal for CO2
Middle muon
HEX is located at PP2 Ex-TRT space available
(more? Other f?), Needs to be thermally
neutral. Plant stage uses existing transfer
network underneath inner muon system. Throttling,
back pressure regulation and heater close to HEX
? accessible and moderate radiation. Detector
stage uses new, insulated pipes from PP2 along
calorimeter endplate to ID. Pump close to PP2 ?
accessible and moderate radiation, but in
magnetic field No heaters or further HEXs
needed If we need throttle, it should also be
located close to HEX for access, if the control
allows.
Access
Inner muon
Calorimeter
ID
Conceptual, not to scale
Georg Vihausser Presented at Thermal
Management WG 10.06.2008
4th Trento Workshop, D. Ferrère
39
40
CO2 Cooling
Chilled water
Critical Point 76 bar, 31oC
Service room
60 bar, 20oC
Detector/Cavern
10 bar, -40oC
Triple Point 6 bar, -56oC
4th Trento Workshop, D. Ferrère
40