FPIX2 The BTeV Pixel Readout Chip

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FPIX2 The BTeV Pixel Readout Chip

• David Christian Fermilab
• Vertex 2003
• September 18, 2003 Windermere, UK

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Outline

• Readout chip requirements.
• Description of almost-final chip (FPIX2).
• Bench tests of FPIX2.
• Bench tests of hybrids (SINTEF sensor FPIX2).
• Bench tests of irradiated hybrids
  (SINTEF sensor FPIX2).

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Chip Designers
Abderrezak Mekkaoui Lead engineer (analog
design overall responsibility)
Jim Hoff Digital design
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Readout Chip Requirements

• Radiation hard.
• Optimized for 132 ns between beam crossings (264,
  396).
• Able to tolerate large sensor leakage current.
• Very high speed zero-suppressed readout.
• Lowest level trigger is pixel based ? all data
  from every crossing must be read out.
• Spectrometer design luminosity 15 MHz
  interaction rate.
• Pixel readout chip requirement minimal data
  loss at 45 MHz interaction rate.

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Radiation Hard

• 0.25m CMOS design started in 1998 verified in a
  series of small test chips.
• Tested to 87 Mrad with no degradation in analog
  performance and only minor changes required to
  bias conditions.
• Digital cells insensitive to total dose.
• No latch-up, no gate rupture.
• Single event upset cross sections measured,
  typically lt 10-15 cm-2 per bit.
• Measured with 200 MeV protons about the same for
  MIPs.
• Expected upset rates 10 pixel kill bits/hr, 2
  DAC register bits/hr, 1 data serializer bit/hr.
• Will reload kill pattern each fill, monitor
  other registers reset as necessary (can be done
  without interrupting data taking for most errors).

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Optimized for 132 ns crossing time

• Timewalk is much less of a problem than at the
  LHC.
• Can minimize (FE noise ? Disc. threshold
  dispersion) without trim DACs in every pixel.
• Allows low discrimination levels (lt3000 e-)

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Tolerate large leakage current

• Separate control of return-to-baseline time and
  leakage current compensation.

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Very high speed readout

• Data kept in pixels until it is serialized and
  transmitted off chip no buffer memory.
• Occupancy varies more than a factor of ten from
  the corner of the detector closest to the beam to
  the corners furthest from the beam ? Flexible
  serial data output interface allows the use of 1,
  2, 4, or 6 output links (each 140 Mbps).

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FPIX2 Block Diagram
Pixel Unit Cells (22 columns of 128 rows each)
Core
Fabricated by TSMC (through MOSIS). Received
early 2003. Only bias voltages required are 2.5V
ground. All I/O is LVDS.
End-of-Column logic (22 copies)
Core Logic
DACs
Next Word Block
Clock Control Logic
Data Output Interface
Programmable Registers
Word Serializer
Programming Interface
Steering Logic
MCA/MCB (Readout Clock)
BCO Clock
Input/Output
High Speed Output
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FPIX2 Layout
Debugging Outputs
Pixel array End-of-Column Logic e Core
128x22 Pixel array
End-of-Column Logic
Registers and DACs
Data Output Interface
Command Interface
LVDS Drivers and I/O pads
Internal bond pads for Chip ID
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Pixel Unit Cell
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Pixel Cells (four 50 x 400 mm cells)
12 µm bump pads
Preamp
2nd stage disc
Kill/ inject
ADC encoder
Digital interface
ADC
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FPIX2 Version A,B and C

• Three versions fabricated by TSMC, all with the
  same digital logic, but with different analog
  cells.
• Version A
• Unchanged from smaller test chips.
• Version B
• Same preamplifier as in version A.
• Second amplifier stage and discriminator
  optimized for TSMC.
• Version C
• Preamplifier with higher gain (lower Cf)
  optimized for TSMC.
• Added unity buffer between 1st and 2nd stage.
• Modified 2nd stage and discriminators as in
  Version B.

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Results at a glance

• Version A works as expected.
• Version B and C work almost as expected except
  for some oscillation problems when biased at
  nominal conditions. Origin of problem still under
  investigation.
• Readout and control perform as expected in all
  versions.
• Readout bandwidth of more than 840Mbps
  achieved.
• No Xtalk observed. Analog performance
  independent of number of communication lines used
  (1,2,4 or 6).
• The following test results are for
  non-hybridized chips (0 input cap).

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Measured Noise
Expected to be 100 e- when connected to a sensor
pixel
Same amp. as Ver. A
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Measured Threshold Dispersion
First prototype fabricated in CERN process had
sth 190 e-.
Amp. disc. optimized, preamp gain increased
(dynamic range reduced), sth 125 e-.
Disc. optimized for TSMC 231? 176.
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Data Output

• Data is driven off of a hit pixel onto the Core
  output bus, which is 23 bits wide. The data word
  consists of the information generated in the
  pixel unit cell (7 bit row number, and 3 bit ADC
  value), plus a 5 bit column number and an 8 bit
  BCO number, which are added by the end of column
  logic.
• The Data Output Interface latches data from the
  Core output bus on the falling edge of the
  readout clock, serializes the data, and drives it
  off chip.

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Output Data Format

• Five bits are used to encode 22 columns. The
  column numbering scheme has no column number
  ending in 00. This ensures that a data word can
  never have 0s in b01 b13. This feature
  distinguishes a data word from a sync/status
  word.
• Synchronization between the FPIX2 and the Pixel
  Data Combiner Board is established and maintained
  using the sync/status word. Whenever no data
  is available for output, the FPIX2 transmits the
  sync/status word. At least two sync/status words
  are guaranteed to be output every time the column
  number decreases. In addition, 23 bit hit data
  is transferred using a 24 bit word. The PDCB
  uses the word mark bit as a sync check on every
  word transfer.

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RCLK and SCLK
 

• The core readout clock (RCLK) is derived from the
  serial clock (SCLK). SCLK is constructed from
  external clocks and is nominally 140 MHz.
• The frequency of RCLK depends on the number of
  output pairs being used. This relationship means
  that no buffer memory is required in the Data
  Output Interface.

35 MHz 4.6/132 ns
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70 MHz clock
This result is from a smaller test chip (used for
dynamic SEU measurement).
140 Mbps 64 kbit random pattern after 50 feet of
flat twisted-pair cable.
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FPIX2 Hybrids

• 4 single chip hybrids recd from AIT.
• SINTEF sensors (160x18), Indium bumps
• 3 out of 4 have obvious damage to wire bonding
  pads.
• The 4th FPIX2 (ver. A) oscillates unless almost
  all pixels are killed.

No Al on most pads
Al
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Tesla p-spray sensors

• Pixel copied from ATLAS.
• Arrays match FPIX2 (128x22).
• Modules for BTeV baseline design 4x, 5x, 6x,
  8x.
• 600m pixels between chips.
• No ganged pixels.
• 1x modules some smaller.
• Contract with VTT for solder bumping should
  receive hybrids by Christmas.

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The End.
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Damage to wire bonds
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