Background

1
Background

• Program must be brought into memory and placed
  within a process for it to be run.
• Input queue collection of processes on the disk
  that are waiting to be brought into memory to run
  the program.
• User programs go through several steps before
  being run.

2
Binding of Instructions and Data to Memory

• Compile time If memory location known a priori,
  absolute code can be generated must recompile
  code if starting location changes.
• Load time Must generate relocatable code if
  memory location is not known at compile time.

3

• Execution time Binding delayed until run time
  if the process can be moved during its execution
  from one memory segment to another. Need
  hardware support for address maps (e.g., base and
  limit registers).

4
Logical vs. Physical Address Space

• The concept of a logical address space that is
  bound to a separate physical address space is
  central to proper memory management.
• Logical address generated by the CPU also
  referred to as virtual address.
• Physical address address seen by the memory
  unit.
• Logical and physical addresses are the same in
  compile-time and load-time address-binding
  schemes logical (virtual) and physical addresses
  differ in execution-time address-binding scheme.

5
Memory-Management Unit (MMU)

• Hardware device that maps virtual to physical
  address.
• In MMU scheme, the value in the relocation
  register is added to every address generated by a
  user process at the time it is sent to memory.
• The user program deals with logical addresses it
  never sees the real physical addresses.

6
Dynamic relocation using a relocation register
7
Dynamic loading to reduce memory requirements

• Routine is not loaded until it is called
• Better memory-space utilization unused routine
  is never loaded.
• Useful when large amounts of code are needed to
  handle infrequently occurring cases.

8
Dynamic Linking

• Linking postponed until execution time.
• Small piece of code, stub, used to locate the
  appropriate memory-resident library routine.
• Stub replaces itself with the address of the
  routine, and executes the routine.
• Operating system needed to check if routine is in
  processes memory address.
• Dynamic linking is particularly useful for
  libraries.

9
Overlays

• Keep in memory only those instructions and data
  that are needed at any given time.
• Needed when process is larger than amount of
  memory allocated to it.
• Implemented by user, no special support needed
  from operating system, programming design of
  overlay structure is complex

10
Swapping

• A process can be swapped temporarily out of
  memory to a backing store, and then brought back
  into memory for continued execution.
• Backing store fast disk large enough to
  accommodate copies of all memory images for all
  users must provide direct access to these memory
  images.

11
Schematic View of Swapping
12
Contiguous Allocation

• Main memory usually into two partitions
• Resident operating system, usually held in low
  memory with interrupt vector.
• User processes then held in high memory.
• Single-partition allocation
• Relocation-register scheme used to protect user
  processes from each other, and from changing
  operating-system code and data.
• Relocation register contains value of smallest
  physical address limit register contains range
  of logical addresses each logical address must
  be less than the limit register.

13
Hardware Support for Relocation and Limit
Registers
14
Contiguous Allocation (Cont.)

• Multiple-partition allocation
• Hole block of available memory holes of
  various size are scattered throughout memory.
• When a process arrives, it is allocated memory
  from a hole large enough to accommodate it.
• Operating system maintains information abouta)
  allocated partitions b) free partitions (hole)

15
OS
process 5
process 8
process 2
16
OS
process 5
process 8
process 2
17
OS
process 5
process 8
process 2
18
OS
process 5
process 8
process 2
19
Fragmentation

• External Fragmentation total memory space
  exists to satisfy a request, but it is not
  contiguous.
• Internal Fragmentation allocated memory may be
  slightly larger than requested memory this size
  difference is memory internal to a partition, but
  not being used.

20
Fragmentation

• Reduce external fragmentation by compaction
• Shuffle memory contents to place all free memory
  together in one large block.
• Compaction is possible only if relocation is
  dynamic, and is done at execution time.

21
Paging

• Logical address space of a process can be
  noncontiguous process is allocated physical
  memory whenever the latter is available.
• Divide physical memory into fixed-sized blocks
  called frames (size is power of 2, between 512
  bytes and 16MB bytes).
• Divide logical memory (i.e., memory addresses
  generated by CPU) into blocks of same size called
  pages.

22
Paging

• OS keeps track of all free frames.
• To run a program of size n pages, need to find n
  free frames and load program.
• Set up a page table to translate logical to
  physical addresses.
• Fragmentation?

23
Paging

• OS keeps track of all free frames.
• To run a program of size n pages, need to find n
  free frames and load program.
• Set up a page table to translate logical to
  physical addresses.
• Fragmentation? Possible to have internal
  fragmentation, not external.

24
Address Translation Scheme

• Address generated by CPU is divided into
• Page number (p) used as an index into a page
  table which contains base address of each page in
  physical memory.
• Page offset (d) concatenated with base address
  to determine the physical memory address that is
  sent to the memory unit.

25
Paging System Example

• Memory consists of 32 Page Frames.
• Pages are 1024 bytes.
• How many bits in physical address?

26
Paging System Example

• Memory consists of 32 Page Frames.
• Pages are 1024 bytes.
• How many bits in physical address?
• 1) How many bits needed to access all pages?

27
Paging System Example

• Memory consists of 32 Page Frames.
• Pages are 1024 bytes.
• How many bits in physical address?
• 1) How many bits needed to access all pages? 5
  25 32.

28
Paging System Example

• Memory consists of 32 Page Frames.
• Pages are 1024 bytes.
• How many bits in physical address?
• 1) How many bits needed to access all pages? 5
  25 32.
• 2) How many bits needed to access all memory
  locations within a page?

29
Paging System Example

• Memory consists of 32 Page Frames.
• Pages are 1024 bytes.
• How many bits in physical address?
• 1) How many bits needed to access all pages?
• 5 25 32.
• 2) How many bits needed to access all memory
  locations within a page?
• 10 210 1024.
• This machine using 15 bit addresses.

30
Paging System Example

• Compiler generates relative (or logical)
  addresses.
• Relative to the beginning of the program.
• Same number of bits in physical and logical
  addresses.
• Assume process P0 consists of 5096 bytes.
• Consider variable located at relative address
  1029. 000010000000101

31
Physical Memory
Process P0 5096 bytes. How many pages in logical
address space?
0 1 2
29
30 31
32
Physical Memory
Process P0 5096 bytes. How many pages in logical
address space? 5
0 1 2
29
30 31
33
Physical Memory
Process P0 5096 bytes. Logical Address space.
0 1 2
0
1
Contiguous
2
29
3
30 31
4
34
Process P0 5096 bytes. Logical Address space.
What is page number and offset within page for
logical address 1029?
0
1
Contiguous
2
3
4
35
Process P0 5096 bytes. Logical Address space.
What is page number and offset within page for
logical address 1029? Pages are 1024 bytes, so
1029 falls in logical page 1 with offset of 5.
0
1
2
Contiguous
3
4
36
Physical Memory
Process P0 5096 bytes. Logical Address space.
0 1 2
P0.0

1
0
1
2
29
3
30 31
4
37
Physical Memory
Process P0s logical address space.
0 1 2
P0.0

1
0
P0.1
1
3
2
29
3
30 31
4
38
Physical Memory
Process P0 5096 bytes. Logical Address space.
0 1 2
P0.2
P0.0

1
0
P0.1
3
1
3
2
0
29
3
30 31
4
39
Physical Memory
Process P0 5096 bytes. Logical Address space.
0 1 2
P0.2
P0.0

1
0
P0.1
3
1
3
2
0
29
3
30
30 31
P0.3
4
40
Physical Memory
Process P0 5096 bytes. Logical Address space.
1
0
1
3
2
0
3
30
4
2
41
Physical Memory
This is the Page Table for process P0. Maps
logical pages to physical pages.
42
Physical Memory

• Frame Physical Ad.
• 0 0 - 1023
• 1 1024 - 2047
• 2048 3071
• 3072 4095

Logical address 1029 stored in physical location
3077.
43
Page Table for Process P0
CPU generates Logical Address 1029.
000010000000101 Address broken into page
numberoffset within page.

44
Page Table for Process P0
00001 0000000101

Page Offset within page.
45
Page Table for Process P0
00001 0000000101

Page Offset within page.
How it works Page number used as index into page
table.
46
Index into Page Table
00001
00001 0000000101

Page Offset
47
Index into Page Table
00001
00011 0000000101 3077

Physical page number concatenated with offset is
physical address.
48
Paging Examples

• Assume a page size of 1K and a 15-bit logical
  address space.
• How many pages are in the system?

49
Paging Examples

• Assume a page size of 1K and a 15-bit logical
  address space.
• How many pages are in the system?
• How many bits are required to address each
  byte within a 1024-byte page?

50
Paging Examples

• Assume a page size of 1K and a 15-bit logical
  address space.
• How many pages are in the system?
• How many bits are required to address each
  byte within a 1024-byte page? 10 (210 1024).
• This leaves 5 bits for page number.
• So, How many pages are in the system?

51
More Paging Examples

• Assume a page size of 1K and a 15-bit logical
  address space.
• How many pages are in the system?
• How many bits are required to address each
  byte within a 1024-byte page? 10 (210 1024).
• This leaves 5 bits for page number.
• So, How many pages are in the system?
• 32 (25 32)

52

• Now consider a 15-bit address space with 8
  logical pages. How large are the pages?

53

• Assuming a 15-bit address space with 8 logical
  pages. How large are the pages?
• Answer 212 4K.
• It takes 3 bits to reference 8 logical pages (23
  8).
• This leaves 12 bits for the page size and thus
  pages are 212.

54
Assume a 15-bit address space with a page size of
1K. (5 bits for page, 10 for offset). What is
the physical address to which logical address
2049 will be mapped?
Page Table for P0
Logical Pages
0 1 2 3 4
8
0 3 X (not used) X (not used)
55
Consider logical address 2049 and the following
page table for some process P0. Assume a 15-bit
address space with a page size of 1K. What is
the physical address to which logical address
2049 will be mapped?
Logical Pages
Step 1. Convert logical address to
binary Logical address 000100000000001
0 1 2 3 4
8
0 3
56
Logical Pages
Step2. Determine the logical page number Since
there are 5-bits allocated to the logical page,
the address is broken up as follows 00010
0000000001 Logical page number offset within
page
0 1 2 3 4
57
00010
00011
Step 3. Use logical page number as an index into
the page table to get physical page number.
Logical Address 00010 0000000001
58
00010
000110000000001
Step 4. Concatenate offset with physical page
frame number Logical Address 00010 0000000001
59
0
0 1 2 3 4
1024
2048
3072

• P0.2

4096
000110000000001 3073
60
0 1 2 3 4
0
1024
P1.2 P1.0
2048

1. P0.2

4096
P2.0
000110000000001 3073
Multiple processes have their pages also in
memory.
61
Address Translation Architecture
62
Yet Another Example
63
Implementation of Page Table

• Problem Each instruction requires two memory
  accesses.
• One to access page table
• One to access physical page
• VERY slow

64
Implementation of Page Table

• Solved by the use of a special fast-lookup
  hardware cache called
• associative memory or translation look-aside
  buffers (TLBs)

65
Associative Memory

• Associative memory parallel search
• Address translation (Page Num, Page Frame)

66
Associative Memory

• If Page Num is in associative register, get frame
  out
• TLB Hit
• Otherwise get frame from page table in memory
• TLB Miss

67
Paging Hardware With TLB
68
Memory Protection

• Memory protection implemented by associating
  protection bit with each frame.
• Valid-invalid bit attached to each entry in the
  page table
• valid indicates that the associated page is in
  the process logical address space, and is thus a
  legal page.
• invalid indicates that the page is not in the
  process logical address space.

69
Valid (v) or Invalid (i) Bit In A Page Table
70
Implementation of Page Table

• Page table is kept in main memory.
• Page-table base register (PTBR) points to the
  page table.
• Page-table length register (PRLR) indicates size
  of the page table.
• In this scheme every data/instruction access
  requires two memory accesses. One for the page
  table and one for the data/instruction.

71
Page Table Implementation Issues

• Consider 32-bit address space with 4K pages.
• 232/212 pages 220 pages. Each entry 4 bytes.
• Need 4 MB for each processes page table (in worst
  case).
• Consider logical address space of 64-bit machines
  with 4K pages (212).
• 264/212 pages (252 pages). Four byte entry
  gives 254 MB for each processes page table (in
  the worst case).

72
Page Table Implementation Issues

• Consider 32-bit address space with 4K pages.
• 232/212 pages 220 pages. Each entry 4 bytes.
• Need 4 MB for each processes page table (in worst
  case).
• Consider logical address space of 64-bit machines
  with 4K pages (212).
• 264/212 pages (252 pages). Four byte entry
  gives 254 MB for each processes page table (in
  the worst case).
• If anyone asks, 254 is a big number.

73
Other Page Table Structures

• Hierarchical Paging
• Hashed Page Tables
• Inverted Page Tables

74
Hierarchical Page Tables

• One way to deal with large page tables is to
  divide the page table into smaller pieces. The
  page table itself is paged.
• That is, have to use a paging mechanism to find
  the individual pages of the page table.
• A simple technique is a two-level page table.

75
Two-Level Paging Example

• A logical address (on 32-bit machine with 4K page
  size) is divided into
• a page number consisting of 20 bits.
• a page offset consisting of 12 bits.
• In a two-level paging system, the 20-bit page
  number is divided between an outer page table
  (termed a page directory) and an inner page table
  that has the number of the actual physical page
  frame.

76
Two-Level Paging Example

• Pi is an index into the page directory.
• This contains the base address of one page of
  the processes page table.
• P2 is a displacement into this page of the
  processes page table.

77
Address-Translation Scheme

• Address-translation scheme for a two-level 32-bit
  paging architecture. Each page of the page table
  maps 1024 virtual pages to physical page frames.

78
Physical Memory
Frame 0 Frame 1 Frame 2
Page 1 of PT
Outer Page Table (Page Directory).
Page 0 of PT
Frame N
79
Physical Memory
Assume Logical Address 0000000001 0000000010
110000110001
P0 P1 D
Frame 0 Frame 1 Frame 2
Frame N
80
Physical Memory
Assume Logical Address 0000000010
110000110001 P1 D
0000000001
Frame 0 Frame 1 Frame 2
Frame N
81
Physical Memory
Assume Logical Address 0000000010
110000110001 P1 D
0000000001
Frame 0 Frame 1 Frame 2
Page 1 of PT
Outer Page Table (Page Directory).
Frame N
82
Physical Memory
Assume Logical Address 110000110001 D
0000000001
Frame 0 Frame 1 Frame 2
0000000010
Page 1 of PT
Outer Page Table (Page Directory).
Frame N
83
Physical Memory
Assume Logical Address
D
110000110001
0000000001
Frame 0 Frame 1 Frame 2
0000000010
Page 1 of PT
Outer Page Table (Page Directory).
Frame N
84
Physical Memory
Assume Logical Address
0000000001
Frame 0 Frame 1 Frame 2
0000000010
d
110000110001
Page 1 of PT
Outer Page Table (Page Directory).
Frame N
85
Inverted Page Table

• One entry for each real page of memory.
• Virtual address is now ltpid, virtual page,
  offsetgt
• PT Entry consists of the virtual address of the
  page stored in that real memory location, process
  id.
• What is the maximum size of the inverted page
  table?
• Decreases memory needed to store each page table,
  but increases time needed to search the table
  when a page reference occurs.
• Use hash table to limit the search to one or at
  most a few page-table entries.

86
Inverted Page Table Architecture
87
Shared Pages

• Shared code
• One copy of read-only (reentrant) code shared
  among processes (i.e., text editors, compilers,
  window systems).
• Reentrant code Non-Self-Modifying code.
• Each users page table maps to the same physical
  location.
• Private code and data
• Each process keeps a separate copy of its own
  code and data.
• These pages can be mapped to any available page
  frame.

88
Shared Pages Example
89
Shared Pages

• Example of system that uses shared pages for
  multiple users?

90
Shared Pages

• Example of system that uses shared pages for
  multiple users?
• Windows The DLLs are shared among all processes.

91
Shared Pages

• Example of system that uses shared pages for
  multiple users?
• Windows The DLLs are shared among all processes.
  
• How can the paging mechanism protect the shared
  pages (i.e, no process can write to the page)?

92
Shared Pages

• Example of system that uses shared pages for
  multiple users?
• Windows The DLLs are shared among all processes.
  
• How can the paging mechanism protect the shared
  pages (i.e, no process can write to the page)?
• Provide additional protection bits to the page
  table entry (i.e., permissions for the use of the
  shared page.

93
Shared Pages

• Example of system that uses shared pages for
  multiple users?
• Windows The DLLs are shared among all processes.
  
• How can the paging mechanism protect the shared
  pages (i.e, no process can write to the page)?
• Provide additional protection bits to the page
  table entry (i.e., permissions for the use of the
  shared page.
• How can shared memory between processes be
  implemented?

94
Shared Pages

• Example of system that uses shared pages for
  multiple users?
• Windows The DLLs are shared among all processes.
  
• How can the paging mechanism protect the shared
  pages (i.e, no process can write to the page)?
• Provide additional protection bits to the page
  table entry (i.e., permissions for the use of the
  shared page.
• How can shared memory between processes be
  implemented?
• Have two processes page table pointing to the
  same physical page frame.
• Allow read/write access to the shared pages.

95
Segmentation

• Memory-management scheme that supports user view
  of memory.
• A program is a collection of segments. A segment
  is a logical unit such as
• main program,
• procedure,
• function,
• method,
• object,
• local variables, global variables,
• common block,
• stack,
• symbol table, arrays

96
(No Transcript)
97
Logical View of Segmentation
physical memory space
user space
98
Segmentation Architecture

• Logical address consists of a two tuple
• ltsegment-number, offsetgt
• Segment table maps two-dimensional physical
  addresses each table entry has
• base contains the starting physical address
  where the segments reside in memory.
• limit specifies the length of the segment.
• Segment-table base register (STBR) points to the
  segment tables location in memory.
• Segment-table length register (STLR) indicates
  number of segments used by a program
• segment number s is legal if s
  lt STLR.

99
Segmentation Hardware