Combinational Synthesis

1
Combinational Synthesis

• ELEC 311
• Digital Logic and Circuits
• Dr. Ron Hayne
• Images Courtesy of John Wakerly and Prentice-Hall

2
Alarm Word Problem

• The ALARM output is 1 if the PANIC input is 1, or
  if the ENABLE input is 1, the EXITING input is 0,
  and the house is not secure.
• ALARM PANIC (ENABLE EXITING' SECURE')
• The house is secure if the WINDOW, DOOR, and
  GARAGE inputs are all 1.
• SECURE WINDOW DOOR GARAGE

3
Alarm Circuit Realization

• ALARM PANIC (ENABLE EXITING' (WINDOW
  DOOR GARAGE)')

4
Sum-of-Products Realization

• ALARM PANIC (ENABLE EXITING' WINDOW')
  (ENABLE EXITING' DOOR') (ENABLE
  EXITING' GARAGE')

5
DeMorgans Theorems

• T13

• T13'

6
NAND-NAND Realizations

• Sum-of-Products
• Two-level AND-OR
• Equivalent NAND-NAND

7
NAND-NAND Realizations
8
NOR-NOR Realizations

• Product-of-Sums
• Two-level OR-AND
• Equivalent NOR-NOR

9
Combinational Minimization

• Reduce cost of two-level circuits
• Minimize number of first-level gates
• Minimize number of inputs on first-level gates
• Minimize number of inputs on second-level gates
• Based on Adjacency Theorem (Combining)
• T10 (X Y) (X Y') X
• T10' (X Y) (X Y') X

10
Karnaugh Map
F SX,Y,Z(3,7) F (X' Y Z) (X Y Z) F
Y Z
11
4-variable K-map
12
Terminology

• Minterm
• Implicant
• Cover
• Prime Implicant
• Distinguished 1-cell
• Essential Prime Implicant
• Secondary Prime Implicant
• Minimal Sum

13
Methodology

• Minimal Sum
• Essential Prime Implicants
• Secondary Prime Implicants
• Minimal Cover

14
Example
F (Y Z) (X Y) (W X' Z)
(W X Z')
F SW,X,Y,Z(3,6,7,9,11,12,14,15)
15
Another Example
F (W' Y Z') (W X' Y') (X
Y' Z) (W X Y)
F SW,X,Y,Z(2,5,6,8,9,13,14,15)
16
Design Example
17
7-Segment Display Numbers
18
BCD to 7-Seg. Truth Table
19
BCD to 7-Seg. Truth Table
20
Minterm Form of Outputs
A Sx1,x2,x3,x4(0,2,3,5,6,7,8,9) d(10-15) B
Sx1,x2,x3,x4(0,1,2,3,4,7,8,9) d(10-15) C
Sx1,z2,x3,x4(0,1,3-9) d(10-15) D
Sx1,x2,x3,x4(0,2,3,5,6,8,9) d(10-15) E
Sx1,x2,x3,x4(0,2,6,8) d(10-15) F
Sx1,x2,x3,x4(0,4,5,6,8,9) d(10-15) G
Sx1,x2,x3,x4(2,3,4,5,6,8,9) d(10-15)

21
Output A
A x3 x1 (x2 x4) (x2' x4')
A Sx1,x2,x3,x4(0,2,3,5,6,7,8,9) d(10-15)
22
Output B
B x2' (x3' x4') (x3 x4)
B Sx1,x2,x3,x4(0,1,2,3,4,7,8,9) d(10-15)
23
Minimized Logic Equations

• A x1 x3 (x2 x4) (x2' x4')
• B x2' (x3 x4) (x3' x4')
• C x2 x3' x4
• D x1 (x2' x3) (x3 x4') (x2' x4')
  (x2 x3' x4)
• E (x2' x4') (x3 x4')
• F x1 (x2 x3') (x3' x4') (x2 x4')
• G x1 (x2 x3') (x2' x3) (x3 x4')

24
Summary

• Word Problem
• Boolean Equation
• Circuit Realization
• Two-Level Circuit Realizations
• SOP (AND-OR) NAND-NAND
• POS (OR-AND) NOR-NOR
• Combinational Minimization
• Karnaugh Maps
• Dont Cares