GTU Architecture

1
MCM tests (Sep 07-Feb 08), available wafers Long
ADC mode of operation Software tools Number of
samples and input pipeline Pretrigger phase
calibration
2
MCMs Tested by SwissBit
Sep 2007 to Feb 2008 3852 tests Number of
different MCMs 3679 Number of MCMs with variable
ChipId 61 Number of MCMs with worse/better/same/tw
ice results/ 36 / 6 / 106 / 148 Number of MCMs
in the last test with results BAD 60 GOOD 3282
CM 3 BM 305 NM 29 Correlation matrix, vertical
first test horizontal second test
BAD2 GOOD2 CM2 BM2 NM2
BAD1 0 0 0 0
0 GOOD1 7 99 0
29 0 CM1 0 0
0 0 0 BM1
0 6 0 7 0
NM1 0 0 0 0
0 From Oct 2007 to Feb 2008 310 MCMs
Number of different MCMs 87 Number of MCMs in
the last test with results BAD 0 GOOD 86 CM 0
BM 1 NM 0
3
Wafer test results
Production run
Tested Usable
Preproduction (25 wafers) 14324 5056
35 Feb 2006 (25 wafers) 14400 8143
57 Jun 2006 (49 wafers) 28006
24018 86 Sep 2006 (49 wafers) 28212
24600 87 Jan 2007 (3 wafers) 1728
1568 91 Mar 2007_1 (25 wafers) 14381
11044 77 Mar 2007_2 (25 wafers) 14366
11927 83 All
115417 86356 75
We have about 40,000 unbonded TRAPs (2007.09)
4
Long ADC mode
24k samples 1 ADC ch OR 12k samples 2 ADC
ch (same CPU) OR 8k samples 2 ADC ch (diff.
CPUs) OR 4k samples 22 ADC ch (2 CPUs)
2 kHz
2 ms
5
Long ADC mode decimation filter
Decimation filter 1x .. 4095x to extend the
range 12k data points Each MCM can be programmed
independently Start via SCSN or
Pretrigger Readout via SCSN
50 Hz
100ms
6
Small software tools
gt tdiff_cnf sc_send_rob.dat 2 sc_send_rob.dat
3 0x0a03 SMMODE 0x0000008a
0x0000b08a 0x0c06 C14CPUA 0x0003002f
0x0003002e 0x0d43 NTRO 0x0003fffc
0x0001fe21 0x0d44 NRRO 0x0003fffc
0x0001fe21 0x3050 ADCMSK 0x001ffff8
0x001fffff Found 5 difference(s)! gt tdiff_dm
sc_send_rob.dat 2 sc_send_rob.dat 15 0xc020
0x00000007 0x00000005 0xc021 0x0006c000
0x00048000 Found 2 difference(s)! gt tdump_cnf
sc_send_rob.dat 2 SML0 0x0000404b SML1
0x000042bc SML2 0x0000422b SMMODE
0x0000008a NITM0 0x0000019a ...
gt taddr A Not found! Searching for names
beginning with A Address hex/dec Name ResetVal
Nbits 0x0a2e 2606 ADCEN 0x00000007
5 0x0a3f 2623 ARBTIM 0x00000000
4 0x3050 12368 ADCMSK 0x001fffff
21 0x3051 12369 ADCINB 0x00000002
2 0x3052 12370 ADCDAC 0x00000010
5 0x3053 12371 ADCPAR 0x000195ef
18 0x3054 12372 ADCTST 0x00000000
2 0x0a2f 2607 ADCENSS Found 8 name(s)
beginning with A gt taddr ADCDAC Address 0x3052
12370 Reset value 0x00000010, number of bits 5
taddr
tdiff
tdump
To be adopted for DCS
Included by Jochen K. in peek/poke
Auto detect pieces of raw data
gt cat evn00000001.txt mini head 0x10001000
Tracklet Endmarker 0x10001000 Tracklet
Endmarker 0xb300508d h0 MajVer 51
(TP0ZS1DT1RS0 Opts F128 Dis.empty MCMs),
MinVer 0, AddHd 1, Sect 8, Plane 2, Chamb 1, Side
1 0x7a2d5c41 h1 Timebins 30, BC 35671, Precnt
1, PrePhase 0 0xa000001c MCM header ROB 2, MCM
00, Event counter 1 0x55fffffc ADCMASK 0x1fffff
number of channels 21, counted ones in the mask
21 0x0781e077 ADC samples 3i, 3i1, 3i2
29 30 30 ... gt mini 0x7A41000C 0x07C1D07A
... 0x7a41000c ADCMASK 0x41000 number of
channels 2, counted ones in the mask 2 0x07c1d07a
ADC samples 3i, 3i1, 3i2 30 29
31 ...
mini
7
Pretrigger ? first sample in TRAP
Pipe5Xtalk ON
Pipe5Xtalk bypassed
Pipe0Xtalk ON
What is our pretrigger latency?
Simple network to see the pretrigger time
8
Last sample stored in the EB
If we want to store Nsamples then the earliest
time to start the CPUs without loosing any
information is at (Nsamples-3)100ns after the
pretrigger. In the configuration this parameter
was Nsamples2 So we gain 500ns. What is our
target Nsamples?
9
Pretrigger phase 9
10
Pretrigger phase 10
11
Pretrigger phase 11
12
Pretrigger phase 0
13
Pretrigger phase 1
14
Pretrigger phase 2
15
Pretrigger phase 3
16
Pretrigger phase 4
17
Pretrigger phase 5
18
Pretrigger phase 6
19
Pretrigger phase 7
20
Spares
21
Pretrigger phase 7
22
Pretrigger phase 9
23
Pretrigger phase 3