HLS Challenges and Proposed Solutions

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HLS Challenges and Proposed Solutions

• Presented by
• Gagan Raj Gupta (2001107)
• Madhur Gupta (2001343)

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Overview

• HLS vs Low level Design Methodology
• HDL CAD Tools
• Benefits
• No commercial tool till now
• Challenging Tasks
• Handling I/O
• Timing Challenges
• Memory Synthesis
• Interconnect cost control
• FSM Delay Estimation

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HLS vs Low Level Design Methodology

• Size of Digital ICs grown
• HDL replace Schematic Design
• Tools for simulation and Synthesis come to help
• Gives hope to chase Moores law of 10X boost in
  productivity

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Benefits of HLS

• Far fewer lines of code
• Faster specification and debugging
• Faster Simulation
• Facilitated by lesser details
• Flexibility in reconfiguring and reusing modules
• Technology independent
• Can be ported to any technology or architecture
  (by varying implementation phase)
• Can meet a wide variety of performance, cost and
  power goals

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Level of Success

• Though efforts are on, No company has yet
  successfully marketed a production-worthy design
  tool flow that can produce and verify high
  quality designs from behavioral descriptions.
• Synopsys has developed Behavioral Compiler.
• There are some efforts in academia like SPARK etc.

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Challenging tasks for HLS

• Handling I/O
• Timing Challenges
• Memory Synthesis
• FSM Delay Estimation

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I/O Scheduling Modes

• Cycle-fixed
• cycle-by-cycle I/O behavior fixed
• not allowed to add extra FSM states!
• Superstate-fixed
• extra states can be added if necessary

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Cycle-fixed scheduling

• wait statements mark cycle boundaries
• I/O operations between two waits are constrained
  to be scheduled into same cycle
• reading and writing of ports
• requires careful analysis!
• Non-I/O operations can be scheduled anywhere
• arithmetic/logical operations

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Contd

• wait ()//S1
• if (x)
• p 1
• wait ()//S2
• else
• p 2
• q 1
• r 1
• wait ()//S3

• if a wait occurs in one branch of a
  conditional, it should also occur in all other
  branches
• is this reasonable?
• why impose this?

Problems with further scheduling
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Contd

• Wait imposed by coding-style restriction
• Leads to only simple actions on each transition
• easier to generate FSM
• New state in FSM
• Unwanted Addition!
• changes behavior

• wait () //S1
• if (x)
• p 1
• wait () //S2
• else
• p 2
• q 1
• wait () //S4
• r 1
• wait () //S3

New State
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Mux inputs before FUs

• If binding follows scheduling...
• an FU may perform different operations in
  different control steps
• MUX implied at FU input
• MUX delay needs to be accounted for by scheduler
• but its too early! Scheduler cannot know MUX size

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Accounting for MUX Delays atFU Inputs

• Solution integrate FU binding with Scheduling
• Iterate Scheduling and Binding
• assume some MUX size (e.g., 4x1) during
  scheduling
• binding is constrained
• if binding cannot find a solution, increase MUX
  size (e.g., 8x1) and reschedule
• Results may be pessimistic
• Worst delay taken for Muxs
• Binding is constrained

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MUX Inputs before Registers

• Similar is the problem because of register
  allocation following scheduling
• The same register may hold results from various
  FUs

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Accounting for MUX Delays atRegister Inputs

• Solution integrate all steps
• Scheduling
• FU binding
• Register Allocation
• assume some MUX size (e.g., 4x1) during
  scheduling
• FU binding and register allocation are
  constrained
• if no solution, increase MUX size (e.g., 8x1) and
  reschedule
• Results may be pessimistic

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In short

• At the time of Scheduling operations are assigned
  to control steps
• Need to know the amount of cycle time available
  to FUs
• Wire delays are unknown at the time of scheduling
• Fanout from FUs vary, Wire lengths are not known
• FSM delays are unknown
• No of states, No of status and control signals
  unknown
• Register-FU interconnection is complex

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Memory Synthesis

• Motivation
• Reduce the complexity of interconnect between
  registers and FUs
• Modeling timing for accessing registers (useful
  during scheduling)
• Optimizing interconnection cost and memory
  utilization cost

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Older Approach

• Two steps
• Grouping the variables or registers to form
  memory modules
• Determining the interconnection between memory
  modules and functional units
• But Optimization is weak because there is no
  precise way to predict the result of step 2
  during step 1

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Newer Approach

• Start with one fictitious large memory
• Assign the variables to the ports and ports to
  the functional units in each control step so as
  to minimize interconnection cost.
• Partition the variables and ports to form memory
  modules, minimizing the cost of memory modules
• Primary focus on minimizing the interconnection
  cost

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Step 1

• Each variable is mapped to a unique register
• At each control step
• Assign the active variable to port (internal
  connection)
• Assign the ports to corresponding functional unit
  terminal (external connection)
• Number of internal connections related to memory
  module cost.
• Heuristics are used (e.g. commutative operations)

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Cost of interconnection

• E is the number of external connections
• I is the number of internal connections
• c is the variable parameter adjusted to reach
  minimal cost

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Step 2

• Construct a graph from Step 1
• Node ? Port
• Edge between two ports ? If there is a variable
  that is accessed through both ports
• Divide the graph into connected components
• Solve the problem of allocating memory modules by
  solving 2-D bin packing problem
• Two dimensions are the number of registers and
  the number of ports in the module

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Algorithm Flow
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Estimating FSM Delay

• FSM description not available before scheduling
• Have to estimate them using high level details,
  as
• Application size
• Application code structure
• Resource constraints
• Number of variables
• Types of operations

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Formulation

• Experimental verification of these suppositions
• Slight modification in earlier formulation (
  Neeraj Singhs work) to estimate delay with more
  precision
• Coefficients determined by the underlying
  technology

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Correlation of identified factors with FSM
characteristics

• Code size ?Number of states
• Number of variables ? Number of control signals (
  increase in registers and mux size)
• Types of operations and resource constraints?
  Increase in number of Control Signals (increase
  in number of control signals for the FUs )

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References

• Kelvin Morris, FPGA and Programmable Logic
  Journal
• Extended Abstract from DAC-33 by Raul Camposano
• Utilization of Multiport Memories in Data Path
  Synthesis Taewhan Kim and C.L.Liu, CS
  Department, UIUC
• Lecture Slides by our teacher Dr.P.R.Panda

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Thank You