Motivation, Performance Analysis and Technology of 3Dimensional ICs

1
Motivation, Performance Analysis and Technology
of 3-Dimensional ICs
Prof. Krishna C. Saraswat Students G. Chandra,
T.-Y. Chiang, Chi On Chui, A. Joshi, P.
Kalavade, P. Kapur and S. Souri Stanford
University, Stanford, CA
Funding MARCO DARPA
2
Outline

• Introduction
• Modeling and simulation
• Limits of 2D Cu/low-k technology
• Assessment of 3D systems performance
• 3D HGI technology development
• Thermal issues
• Conclusion

3
On-chip wires are getting slower
x2 s x1 0.5x R2 R1/s2 4x C2 C1 1x tw2
R2C2y2 tw1/s2 4x

• Measure of Performance Longest interconnect
  delay on the rise (ITRS data)
• Longest interconnect 2XChip edge
• ITRS projects 100nm node (feature size 65nm) as
  interconnect performance limited

4
Will better materials like copper and low-k
dielectrics solve the interconnect problem?
5
Cu Resistivity Effect of Line Width Scaling

• Effect of Cu diffusion Barrier
• Barriers have higher resistivity
• Barriers cant be scaled below a minimum
  thickness
• Consumes larger area as dimensions decrease
• Effect of Electron Scattering
• Reduced mobility as dimensions decrease
• Reduced mobility as chip temperature increases

Barrier
Future
Cu
e
e
Surface scattering
Bulk scattering

• Resistivity of metal wires could be much higher
  than bulk value
• Problem is worse than anticipated in the ITRS
  roadmap

6
Realistic Copper Resistance Modeling
Effect of barrier technology, electron scattering
and operation temperature
Elastic scattering
Diffuse scattering
IPVD
ALD
C PVD
barrier
P 0
Cu
P 1

• Barriers cant be scaled and have high
  resistivity
• Surface electron scattering increases
  resistivity
• Barrierless Cu technology need to be developed
• Problem is worse than anticipated in the ITRS

Kapur and Saraswat IEEE TED, April 2002
7
Semi-global Local Interconnects

Effect of Barrier Deposition Technologies
Temp.100 0C, P0.5, Barrier thickn. 10 nm
C-PVD
PVD
ALD
No Barrier

• Resistivity rises faster for local
• 35 nm node even with ALD resistivitiy 4.2
  (semi-global), 5 ??-cm (local)
• Cu exceeds Al resistivity in future due to higher
  mean free path
• Need for a barrierless technology with P 1

Kapur and Saraswat, IEEE TED, April 2002
8
Resistivity Trends with Best (ALD) Barrier
Technology
Effect of temperature and P (Barrier
Thickness10nm)

• Temperature has a large effect
• Realistic Values at 35nm node P0.5, temp1000C
• - local 5??-cm
• - semi-global 4.2??-cm
• global 3.2??-cm
• Need new ultra cooling mechanisms (lower wire
  temperature)

Kapur and Saraswat IEEE TED, April 2002
9
Summary of resistance per unit length at 35 nm
node
Realistic Cu resistivity with technology
constraints is much higher than the bulk value
10
Can we solve the problem by using more repeaters?
Delay of a line without repeaters
Delay of a line with n repeaters

• A big fraction of the chip area would be occupied
  by repeaters
• Additional power will be consumed by repeaters

11
Repeater Area Penalties
Via Blockage penalty Non-negligible
12
Global Signaling Wire Repeater Power Penalty

• Exorbitant power signaling wires at
• future nodes (50nm)
• Global Wires 60 Watts (p0.55)
• Repeaters 60 Watts (p0.55)
• 120W for just global signaling wires

Delay optimal repeaters double power
consumption of the wire
13
New techniques to minimize the communication
distance/time will be needed to continue the
evolution in integrated electronics

• Minimize wire length
• Better circuit design
• 3-D ICs
• Novel communication mechanisms
• Optical interconnects
• RF wireless interconnects

14
Can Optical Interconnects help?

• Signal wires
• Reduce delay
• Increase bandwidth
• Clock distribution
• Reduce jitter
• Reduce skew
• Reduce clock distribution power (50-60 of total
  power on chip)

15
Optical Vs. Electrical Wires Signaling Delay
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Optical Vs. Electrical Wires Delay

• Optical Interconnects are
• faster than repeated wires
• beyond a length well within
• chip size
• However for Signaling both
• delay and power are important

50nm Node

• 1.8 mW is approximately power
• dissipated by a repeated chip
• edge long wire

Kapur and Saraswat IEEE IITC, June 2002
17
Power breakdown at the 180nm node
Chandra, Kapur and Saraswat, IEEE IITC, June 2002
18
Result scaling of power components
ITRS projections for total power dissipation on
chip
Chandra, Kapur and Saraswat, IEEE IITC, June 2002
19
Power Dissipation Comparisons Between Metal,
Optical and Wireless Clock Distribution
1
1
1
Kapur and Saraswat IEEE IITC, June 2002
Lower Detector Capacitance and higher IOP for
low Receiver power Dissipation
1 Data on metal wires and wireless from Floyd
et al, Proc.IITC, pp. 248-251, 1999.
20
Optical Vs. Electrical Wires Delay Power

• Longer lengths optics both power and delay
  advantage
• Shorter lengths diminishing delay advantage and
  power disadvantage

• With technology node power and delay advantages
  increase for long global wires whose number is
  not large

Alternate architecture using wires more
efficiently (higher SA) can give huge power as
well as delay advantages with optics
Kapur and Saraswat IEEE IITC, June 2002
21
3-D Integration Motivation

• Reduced Chip footprint ? reduced R, L, C
• Reduced latency and power, increased bandwidth
• Integration of heterogeneous technologies ?
  Increased functionality
• Logic, memory, mixed signal, optics

3D
2D
Shorter Wire
Very Long Wire
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Wire-length Distribution of 3-D IC
Microprocessor Example Number of Logic Gates
93.6 million Number of Memory Devices 86.4
million Minimum Feature Size 50 nm Number of
wiring levels, 9 Metal Resistivity,
Copper 1.673e-6 W-cm Dielectric Constant,
Polymer er 2.5
(Revised)
Previous Calculations
Logic
Revised Calculations
Logic
Memory
23
Delay of scaled 3D ICs with multiple Si layers

• Moving repeaters to upper active layers reduces
  delay by 9
• 3D (2 Si layers) shows delay reduction to 62
• Increasing metal layers reduces delay further by
  25
• 3D can alleviate interconnects limits

24
Random redistribution of logic
2D
Random redistribution
Optimized redistribution

• Random redistribution indiscriminate replacement
  of short/long wires with VILICs for generalized
  analysis
• Optimal redistribution only critical paths
  replaced. Dependent on particular IC design
• Conservative analysis expected due to randomizing

25
Technology to fabricate 3D ICs
Objective To develop low thermal budget high
performance CMOS device technology to fabricate
3D HGI systems Approach Low temperature
crystallization of amorphous Si, Ge and SiGe and
device fabrication
26
Novel MOS Structures for 3-D IC Technology
Demonstrated in Recrystallized Si
Lateral Gate-All-Around MOS in Recrystallized
Ultra-thin Si Film
Single Grain MOS by Seeding and Crystallization
9 nm Vertical MOS in Recrystallized Si
SiGe gate

gate dielectric
strained Si interlayer
Seed
unstrained SiGe
channel
source
drain
Ni seeding for simultaneous crystallization and
dopant activation
substrate (oxidized Si wafer)
GSOI MOS
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Pillar MOSFETs in Ni induced crystallized ?-Si
for 3-D ICs
(J. Plummer, Stanford, MARCO MSD)

• Pillar-MOSFETs
• Improved control of the gate on the channel
• Low subthreshold slope
• Improved short channel characteristics
• High packing density
• Channel length decoupled from lithography
• Metal-Induced Crystallization
• Low temperature, low cost, low thermal budget
• Reasonably good crystal quality
• Compatible with 3D integration
• Possible novel device structures

Pillar-MOSFET
NiSi2 assisted crystallization
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Single Crystal Pillar with Metal-Induced
Crystallization
(J. Plummer, Stanford, MARCO MSD)

• Common MIC process produces poly-Si
• Two-step MIC method enables fabrication of
  single-crystalline Si with confined structures

NiSi2 grain growth into a single crystalline
template
single crystalline Si growth
NiSi2 formation
NiSi2
Ni
c-Si
NiSi2
a-Si
a-Si
a-Si
a-Si
Second step NiSi2-mediated SPE
First step single crystalline template formation
Higher temperature (550?C)
Low temperature (400?C), long time
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Ultra-Thin Body Vertical Replacement Double Gate
MOSFET in Recrystallized Si
Goal To develop materials and device technology
to enable fabrication of high performance
vertical double gate MOSFETs compatible with 3D
technology.

• Key Features
• Ultra-thin x-Si body fully depleted
• All critical dimensions (TSi, LG) controlled
  precisely without lithography
• Raised S/D structure for reduced parasitic
  resistance
• Self-aligned SDEs resulting in small parasitic
  capacitances
• High quality back interface, with the possibility
  of a back-gate
• High-K compatible

Drain
Source
Gate
Transistor
S/D
G1
G2
S/D
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TEM Image of UTB-VRG MOSFET Structure
Source
Nitride
LG
Gate layer
Buried oxide
Channel

• Demonstrated the use of a subtractive SPE process
  in the realization of this novel structure
• The SSPE process might also be used to add
  precisely controlled, ultrathin x-Si layers to a
  conventional bulk MOSFET core, creating the
  realistic possibility of 3-D integration

14 nm-thick x-Si body
Nitride
Drain
(Kalavade, et al. Si Nanoelctronics Workshop,
June 2002)
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Ordered Semiconductor Single Nanocrystals on
Amorphous Substrtes
(Fabian Pease Charles Musgrave, MARCO MSD)
PRINCIPLE
VARIOUS APPROACHES
L B
Polymer
ALD
Polymer
SiO2
Low T CVD
Low T CVD
Crystallization
Semiconductor
Semiconductor
Semiconductor
Semiconductor
Polymer
Polymer

• Use LB techniques to deposit initial ordered
  organic template layers.
• Deposit semiconductor directly on LB film using
  low-T CVD.
• Deposit Al2O3 on LB film using ALD and then
  deposit semiconductor on Al2O3 using low-T
  process.
• Grow semiconductor directly on SiO2 and use field
  induced crystallization

32
Monolithically Integrated Optical Receiver
Ge-MSM Ge-TFT

• Advantages with Germanium
• Higher electron/hole mobilities
• Smaller bandgap gt better scalability
• Lower processing temperature
• Compatible with Si technology
• Key Challange
• Require high quality Ge/insulator interface
• GeO2 thermodynamically unstable and water soluble
• Approach
• High-? ultrathin dielectrics, e.g., ZrO2, HfO2 to
  passivate Ge
• Low resistance germanide contacts

Partially funded by DARPA HGI and MARCO IFC
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Integrated Ge Optoelectronic Devices

• Ge MSM photodetectors or Ge PIN photodiodes
• Ge absorbs IR radiation in small thickness
• Can be used in 1.3 - 1.5 µm wavelength range
• l selectivity to Si
• ? No extra circuit noise generated in the bottom
  Si layer in 3D
• Dark current generated from the poorly passivated
  surface would
• be huge, giving low signal-to-noise ratio

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New Materials for Ge MOSFETs
Where Do These New Materials Help? Ichannel ?
charge x source injection velocity ?
(gate oxide cap) x (gate overdrive) vinj ?
Cox (VGS - VT) Esource minj

• High Quality Ge Channel
• ? Mobility enhancement
• ? Complaint with Vsup scaling
• ? Lower processing temp
• Extrinsically,
• Metal Germanosilicide S/D
• ? ? contact resistance

• High-? Gate Dielectrics
• ? ? gate-to-channel coupling
• ? Improved leakage, reliability
• ? ? gate dopant penetration
• Metal Gate Electrode
• ? ? gate poly depletion

35
High- ? Dielectric Technology for Ge-Based MOS
Applications
UV Ozone Oxidation at room temp.

• Physical zirconia thickness 35Å
• Atomically flat Ge surface
• Free of the lower-k and unstable GeO2 interfacial
  layer
• ZrO2 has an amorphous or microcrystalline nature

36
First Demonstration of Ge MOS Devices with High-?
Gate Dielectric

I-V
C-V

• Low temperature process (lt 400C)
• EOT (w.r.t. SiO2) of about 6-10Å, thinnest so far
• Excellent C-V characteristics, hysteresis
  negligible
• Excellent electrical stress reliability,
  uniformity and device yield.
• MOSFET fabrication in progress

(Chui and Saraswat et al., IEEE DRC, Santa
Barbara, June 2002)
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Are there any problems with the concept of 3D
ICs?
I am Hot !
ILD2
Gate
ILD1
Dielectric Constant
Gate
Thermal Conductivity W / mK
Silicon
Heat Flow
Package
Technology Node nm
Heat Sink
38
3D Thermal Analysis of Interconnects
THERMAL ANALYSIS USING SPICE.
THERMAL-ELECTRICAL ANALOGY
Thermal Electrical Temperature T K Voltage V
V Heat q J Charge Q C Heat flux
q W Current I A Thermal resistance RT
K/W Electrical resistance R V/A Thermal
capacitance CT J/K Electrical capacitance
C C/V Heat diffusion RC
transmission line
3-D THERMAL CIRCUIT
EFFECT OF VIAS

• Excellent agreements with experimental and finite
  element analysis (ANSYS)
• Significantly less effort to set up and less CPU
  time
• 3D heat analysis of full chip including via effect

Chiang and Saraswat, VLSI Symp, June 2001
39
3D effects on die temperature

• 3D shows increased die temperature
• Power density strongly affects temperature rise

(T-Y Chiang et al., IEDM, 2001)
40
Integrated Microchannel Cooling for 3D

• Microchannel Thermal Interconnects remove heat
  from targeted areas by means of convective
  boiling
• Detailed modeling for 2D mixed-signal shows that
  temperature uniformity can be achieved for
  conditions of dramatically varying heat flux
• 2D 3D experimental demonstrators in progress
  using plasma etching bonding

Ref Prof. Goodson. (Stanford Univ.)
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Summary

• Conventional Interconnects Challenges and
  Limitations
• Cu effective ? rises dramatically at all tiers.
  Need for a barrierless technology, new ultra
  cooling mechanisms (lower wire temperature) and
  interface technology yielding P values close to 1
  
• Realistic modeling shows that in future delay
  rises significantly even with repeaters
• Interconnect power also rises in future
• Delay optimized repeaters double the wire power
• Alternatives in Future
• 3D technology promising
• Could reduce interconnect delay and power
• Allow heterogeneous integration
• Crystallization by seeding of amorphous
  semiconductors is a promising technology for 3D
  integration
• Optical Interconnects promising for for clocks
  and longer links