DTTC Presentation Template

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Electronics Beyond Nano-scale CMOS

• Shekhar Borkar
• Intel Corp.
• July 27, 2006

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Outline

• Evolution of Electronics to CMOS
• The three tenets
• Technology outlook
• Challenges
• Potential solutions
• Summary

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Evolution of Electronics
Mechanical
Electro-Mechanical
Electronic-VT

• All cross-road technologies show
• Gain
• Signal/Noise
• Scalability

Bipolar
NMOS
CMOS.? ?
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The Three Tenets
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Electro-Mechanical scalingRelays
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Vacuum Tubes
1930s
1920s
1950s 60s
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Semiconductors
The first transistor
Pentium 4
The first integrated circuit
4004
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Benefits of Scaling
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Technology Outlook
High Volume Manufacturing 2004 2006 2008 2010 2012 2014 2016 2018
Technology Node (nm) 90 65 45 32 22 16 11 8
Integration Capacity (BT) 2 4 8 16 32 64 128 256
Delay CV/I scaling 0.7 0.7 gt0.7 Delay scaling will slow down Delay scaling will slow down Delay scaling will slow down Delay scaling will slow down Delay scaling will slow down
Energy/Logic Op scaling gt0.35 gt0.5 gt0.5 Energy scaling will slow down Energy scaling will slow down Energy scaling will slow down Energy scaling will slow down Energy scaling will slow down
Bulk Planar CMOS High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability
Alternate, 3G etc Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability Low Probability High Probability
Variability Medium High Very High Medium High Very High Medium High Very High Medium High Very High Medium High Very High Medium High Very High Medium High Very High Medium High Very High
ILD (K) 3 lt3 Reduce slowly towards 2-2.5 Reduce slowly towards 2-2.5 Reduce slowly towards 2-2.5 Reduce slowly towards 2-2.5 Reduce slowly towards 2-2.5 Reduce slowly towards 2-2.5
RC Delay 1 1 1 1 1 1 1 1
Metal Layers 6-7 7-8 8-9 0.5 to 1 layer per generation 0.5 to 1 layer per generation 0.5 to 1 layer per generation 0.5 to 1 layer per generation 0.5 to 1 layer per generation
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CMOS Research Continues
Technology Generation
90 nm 65 nm 45 nm 32 nm 2004 2006 2008 2010 201
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SiGe S/D Strained Silicon
SiGe S/D Strained Silicon
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CMOSCross Road?
Cross Road False Alarms Cross Road False Alarms Cross Road False Alarms
1 m Short Channel Effects Device Engineering
0.5 m Interconnects More metals, Cu Low K ILD
130 nm SD Leakage Leakage control, avoidance, tolerance
65 nm Gate Leakage Hi-K Metal Gate
22 nm Lithography EUV, Self assembly

lt 1.5nm SD Tunneling ?
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Whats in sight after CMOS?

• Which technology shows gain?
• Satisfactory signal to noise ratio?
• At room temperature?
• Scalability in some shape or form?
• Performance, Energy, Cost
• Research must continue to find one
• Then it will take 10-15 years to mature
• Until then

CMOS will continue
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But With Challenges!
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Yesterdays Freelance Layout
No layout restrictions
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Transistor Orientation Restrictions
Transistor orientation restricted to improve
manufacturing control
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Transistor Width Quantization
Vdd
Vdd
Op
Ip
Op
Vss
Vss
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Todays Unrestricted Routing
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Future Metal Restrictions
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Reliability
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Implications to Reliability

• Extreme variations (Static Dynamic) will result
  in unreliable components
• Impossible to design reliable system as we know
  today
• Transient errors (Soft Errors)
• Gradual errors (Variations)
• Time dependent (Degradation)

Reliable systems with unreliable components
Resilient mArchitectures
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Implications to Design Test

• Design with regular fabric
• One-time-factory testing will be out
• Burn-in to catch chip infant-mortality will not
  be practical
• Test HW will be part of the design
• Dynamically self-test, detect errors,
  reconfigure, adapt

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In a Nut-shell
Yet, deliver high performance in the power cost
envelope
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Recipe for Resiliency

1. Circuit
2. Firmware
3. Platform
4. Software
5. Application

1. Detect
2. Isolate
3. Confine
4. Reconfigure
5. Recover adapt

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Resiliency with Reconfiguration

• Dynamic on-chip testing
• Performance profiling
• Spare hardware
• Binning strategy
• Dynamic, fine grain, performance and power
  management
• Coarse-grain redundancy checking
• Dynamic error detection reconfiguration
• Decommission aging HW, swap with spare

• Dynamically
• Self test detect
• Isolate errors
• Confine
• Reconfigure, and
• Adapt

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Why Bother?
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Summary

• Three tenets Gain, Signal/Noise, Scalability
• Nothing on the horizon satisfies them
• Research must continue to find one
• But until then, CMOS rules
• Several challenges lay ahead, but when have they
  not?