CAD Tutorial: VHDL

1
CAD TutorialVHDL

• Xilinx ISE 5
• Student Edition

2
General Information

• You will be using the Xilinx ISE 5 Student
  Edition and ModelSim tools
• Computer Aided Design (CAD) tools are available
  on most PCs (running Windows XP) in the CEC
  laboratory
• FYI these are student versions of the tools
  widely used in industry for logic design and
  simulation
• Xilinx is the largest vendor of
  Field-Programmable Gate Array (FPGA) devices, a
  type of programmable hardware see
  http//www.xilinx.com for more information
• Accessing the tools
• Start ? Engineering ? Xilinx ISE 5 ? Project
  Navigator
• When turning in assignments, be sure to print
  both your schematic and the waveform from the
  simulation
• Steps are very similar to the Schematic Capture
  Tutorial

3
Starting New Project

• Start Project Navigatorby selecting
• Start
• ? Engineering
• ? Xilinx ISE 5
• ? Project Navigator

File ? New Project
Specifyname and location
SpecifyVirtex 2 and XST VHDL
4
Starting New VHDL Module
Project? New Source
Select VHDL Module
enter name
5
Port Definition Select I/Os
Select correct polarity (input or output)
6
Verify Port Definition
Verify I/Os then select Finish
7
Generated VHDL Skeleton Code
8
Completing the code fill-in architecture
Enter circuit description in the architecture
section between begin and end Behavioral
Save description when finished
9
Simulation

• Steps for generating the testbench and expected
  results are identical for VHDL and schematic
  capture
• Steps for simulating modules are identical as
  well
• The following slides are included as reminders

10
Simulating Circuit
Project? New Source
select test bench waveform
11
Simulation timing
You may use default timing values, or enter 10 in
both and ns for Time Scale to shorten simulation
time
Click OK
12
Specifying Inputs to Circuit
define input waveforms by clicking to create
transitions
note how all combinations of inputs are defined
Window shows generated VHDL code for
testbench (ignore for now)
13
Generating Expected Results
double-click here to generate expected results
expected results shown in HDL Bencher
quit without saving
finally, double-click here to do full simulation
14
Running Simulation
main ModelSim command window
zoom controls
restart and Run all buttons
waveforms appear here