Virtual Memory

1
Virtual Memory
2
Virtual Memory Motivation

• Historically, there were two major motivations
  for virtual memory to allow efficient and safe
  sharing of memory among multiple programs, and to
  remove the programming burden of a small, limited
  amount of main memory.
• PattHenn 04
• a system has been devised to make the core drum
  combination appear to programmer as a single
  level store, the requisite transfers taking place
  automatically
• Kilbum et al.

3
Purpose of Virtual Memory

• Provide sharing
• Automatically manage the M hierarchy (as
  one-level)
• Simplify loading (for relocation)

4
Structure of Virtual Memory
From Processor
To Memory
5
A Paging System
64K virtual address space 32K main memory
Main memory address
Virtual address
4K
4K
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Page Table
Page frame
Virtual page
Main memory Page frame
1 present in main memory, 0 not present in
main memory
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Address Translation
See PH Fig. 7.19 3rd Ed or 5.19 4th Ed
In Virtual Memory, blocks of memory (called
pages) are mapped from one set of address (called
virtual addresses) to another set (called
physical addresses)
8
Page Faults
See PH Fig. 7.22 3rd Ed or 5.22 4th Ed
If the valid bit for a virtual page is off, a
page fault occurs. The operating system must be
given control. Once the operating system gets
control, it must find the page in the next level
of the hierarchy (usually magnetic disk) and
decide where to place the requested page in main
memory.
9
Technology in 2008
See PH Fig. pg. 453 4th Ed
10
Typical ranges of parameters for virtual memory
in 2008
See PH Fig. 5.29 4th Ed
11
Virtual Address Mapping
VIRTUAL ADDRESS
Address within Page
Page Number
Displacement
Base Address of Page
PAGE (in Memory)
12
Terminology

• Page
• Page fault
• Virtual address
• Physical address
• Memory mapping or address translation

13
VM Simplifies Loading

• VM provide relocation function.
• Address mapping allows programs to be load in any
  location in Physical Memory
• Under VM relocation does not need special OS
  hardware support as in the past

14
Address Translation Consideration

• Direct mapping using register sets.
• Indirect mapping using tables.
• Associative mapping of frequently used pages.

15
Design of Virtual Memory

• The Page Table (PT) must have one entry for each
  page in virtual memory!
• How many Pages?
• How large is PT?

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4 Key Design Decisions in VM Design

• Pages should be large enough to amortize the high
  access time. (from 4 kB to 16 kB are typical, and
  some designers are considering size as large as
  64 kB.)
• Organizations that reduce the page fault rate are
  attractive. The primary technique used here is to
  allow flexible placement of pages. (e.g. fully
  associative)

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4 Key Design Decisions in VM Design

• Page fault (misses) in a virtual memory system
  can be handled in software, because the overhead
  will be small compared to the access time to
  disk. Furthermore, the software can afford to
  used clever algorithms for choosing how to place
  pages, because even small reductions in the miss
  rate will pay for the cost of such algorithms.
• Using write-through to manage writes in virtual
  memory will not work since writes take too long.
  Instead, we need a scheme that reduce the number
  of disk writes.

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What happens on a write ?

• Write-through to secondary storage is impractical
  for VM.
• Write-back is used
• Advantages (reduce number of writes to disk,
  amortize the cost).
• Dirty-bit.

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Page Size Selection Constraints

• Efficiency of secondary memory device.
• Page table size.
• Fragmentation (internal) .
• Last part of last page
• Program logic structure
• logic block size 1k 4k
• Table fragmentation Kai, P68
• PT occupies some space

20
Page Size Selection

• PT size.
• Miss ratio.
• PT transfer from disk to memory efficiency.
• Internal fragmentation.
• text
• heap
• stack
• Start-up time of a process - the smaller the
  faster!

3 x 0.5 1.5 times of a page size per process!
21
An Example

• Case 1
• VM page size 512
• VM address space 64 k
• Total virtual page 64k/512 128 pages

22
An Example (cont)

• Case 2
• VM page size 512 VM address space 4G 232
• Total virtual page 8M pages
• If each PTE has 13 bits so total PT size
  (bytes)
• 8M x 4 32M bytes
• Note assuming Main Memory has
• 4M byte or 213
  frames

4G 512
4M 512
222 29
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An Example (cont)

• How about
• VM address space 252 (R-6000)
• (4 Petabytes)
• page size 4K bytes
• so total number of virtual pages

252 212
240
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Techniques for Reducing PT Size

• Set a lower limit, and permit dynamic growth.
• Permit growth from both directions.
• Inverted page table (a hash table).
• Multi-Level page table (segments and pages).
• PT itself can be paged I.e. put PT itself in
  virtual address space (Note some small portion
  of pages should be in main memory and never paged
  out).

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Two level Address mapping
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• Placement
• OS designers always pick lower miss rates vs.
  simpler placement algorithm
• So, fully associativity -
• VM pages can go anywhere in the main M (compare
  with sector cache)
• Question
• Why not use associative hardware?
• ( of PT entries too big!)

27
VM Implementation Issues

• Page faults handling.
• Translation lookahead buffer (TLB)
• Protection issues

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Fast Address Translation

• PT must involve at least two accesses of M for
  each M address
• Improvement
• Store PT in fast registers
• Example Xerox 256 R ?
• TLB
• For multiprogramming, should store pid as part of
  tags in TLB.

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Page Fault Handling

• When a virtual page number is not in TLB, then PT
  in M is accessed (through PTBR) to find the PTE
• If PTE indicates that the page is missing a page
  fault occurs
• Context switch!

30
Making Address translation fast
See PH Fig. 7.23 3rd Ed or 5.23 4th Ed
The TLB acts as a cache on the page table for the
entries that map to physical pages only
31
Typical values for a TLB in 2008
See PH Fig. 5.29 4th Ed
Although the range of values is wide, this is
partially because many of the values that have
shifted over time are related for example, as
caches become larger to overcome larger miss
penalties, block sizes also grow.
32
TLB Design

• Placement policy
• Small TLBs full-associativity can be used
• Large TLBs fully-associativity may be too slow
• Replacement policy sometime even random policy
  is used for speed/simplicity

33
Example FasthMATH
See PH Fig. 7.25 3rd Ed or 5.25 4th Ed
Processing a read or a write-through in the
Intrinsity FastMATH TLB and cache
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PME Page map entry
If s/u 1 - supervisor mode PME(x) C 1-page
PFA modified PME(x) P 1-page is private to
process PME(x) pid is process identification
number PME(x) PFA is page frame address
Virtual to real address translation using page map
35
Translation Look - Aside Buffer

• TLB - miss rate is low
• Clark-Emer data 85 34 times smaller then
  usually cache miss ratio.
• When TLB-miss, the penalty is relatively low
• A TLB miss usually result in a cache fetch.

36
Translation Look - Aside Buffer
contd

• TLB-miss implies higher miss rate for the main
  cache
• TLB translation is process-dependent
• Strategies for context switching
• Tagging by context
• Flushing

complete purge by
context (shared)
No absolute answer
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Integrating VM, TLBs and Caches

• The TLB and cache implement the process of going
  from a virtual address to a data item in the
  Intrinsity Fast MATH.
• This figure shows the organization of the TLB
  and the data cache, assuming a 4 kB page size.
• This diagram focuses on a read.

See PH Fig. 7.24 3rd Ed or 5.24 4th Ed