Chapter 5 The ISA Level

1
Chapter 5The ISA Level

• CS 271 Computer Architecture
• Indiana University Purdue University Fort Wayne

2
The ISA level

• The Instruction Set Architecture (ISA) level
  consists of . . .
• Machine language instructions available to the
  typical user
• No privileged kernel mode instructions
• No operating system service calls
• User accessible registers
• Available data types
• Memory model
• Addressing modes

3
The ISA level

• The ISA level is similar to, but distinct from,
  the assembly language level
• The assembly language level is two levels higher
  than the ISA level
• Includes operating system service calls
• Includes privileged kernel mode instructions in
  addition to machine language instructions
  available at the ISA level

4
ISA level design issues

• Memory
• Registers
• Data types
• Instruction formats
• Levels of I/O support
• Traps and interrupts

5
ISA memory choices

• Cell size?
• Typically a byte
• Word size?
• Typically 4 or 8 bytes
• Word alignment
• Does an 8-byte word need to start at an address
  evenly divisible by 8?

6
Register issues

• Many of the microarchitecture registers are not
  available at the ISA level
• Cache management
• Memory access
• I/O devices
• Hardware control
• RISC architectures generally have more general
  purpose registers than CISC architectures
• Usually 32 or more

7
Register issues

• Typical ISM registers
• General purpose
• Typically referred to as R0, R1, R2, etc.
• Special purpose
• PC, SP, LV, PSW

8
Register issues

• PSW (Processor Status Word)
• Holds condition codes for conditional branches
• For example, N and Z bits
• Mode bit
• User mode
• Kernel mode
• Trace bit
• CPU priority
• Interrupt enable bit

9
Register issues
ROM
RAM
(a) On-chip memory organization for the 8051 (b)
Major 8051 registers.

• The Pentium 4s primary registers

10
Register issues
The UltraSPARC IIIs general registers
11
Data types

• Numeric
• Signed integer
• 8, 16, 32, 64, 128 bit
• Unsigned integer
• Floating point
• BCD (Binary Coded Decimal)

12
Data types

• Non-numeric
• Character
• ASCII
• Unicode
• String
• Machine language instructions usually exist
• Boolean
• 1 Boolean per byte?
• Bit map with 32 Booleans per 4-byte word
• Pointer

13
The Pentium 4 numeric data types. Supported types
are marked with .

• The UltraSPARC III numeric data types

The 8051 numeric data types
14
Instruction formats

• How are instructions coded in the instruction
  stream?
• Typically there is an opcode followed by operands
• A variable number of operands are possible
• Common to have 0, 1, 2, or 3 operands

Four common instruction formats (a)
Zero-address instruction. (b) One-address
instruction (c) Two-address instruction. (d)
Three-address instruction.
15
Instruction formats

• Examples of various numbers of operands

typical operands instruction
interpretation 3 ADD A, B, C
Adds A and B with the result to C A, B,
and C could be memory or regs 2 ADD
A, B Adds A and B with result replacing
B A and B could be memory or regs
1 ADD D D added to an accumulator
register D could be memory or a
register 0 ADD Stack
addressing
16
Instruction formats

• The overall instruction format may be fixed
  length or variable length
• Variable length is typical
• Shorter is better for both opcodes and operands

Some possible relationships between instruction
and word length.
17
Instruction formats

• A fixed-format opcode with n bits allows 2n
  instructions
• A one byte opcode could support 256 instructions
• Opcodes with variable formats offer more
  flexibility
• An example of a variable instruction format is to
  use expanding opcodes
• Expanding opcodes allow trade-offs between opcode
  bits and operand bits

18
Expanding opcode example

• Suppose each ISM instruction has a fixed 16-bit
  size
• This includes the opcode together with any
  operands
• One possible format would be to have . . .
• A 4-bit opcode
• Three 4-bit operands
• Perhaps there are 16 general purpose registers
  and each 4-bit operand is a code for a register

19
Expanding opcode example

• However, in the same 16 bits, it is possible to
  have
• 15 three-operand instructions
• 14 two-operand instructions
• 31 one-operand instructions
• 16 instructions with no operand
• Opcode 15 is interpreted differently than opcodes
  0 through 14
• How this is possible is illustrated on the
  following slide

20
Expanding opcode example
An expanding opcode allowing 15
three-address instructions, 14 two-address
instructions, 31 one-address instructions, and 16
zero-address instructions. The fields marked
xxxx, yyyy, and zzzz are 4-bit address fields.
21
Pentium 4 instruction formats
22
UltraSPARC instruction formats
The original SPARC instruction formats
23
The 8051 instruction formats
24
Operand addressing

• Most bits in an instruction are used for codes
  for operands
• Addressing modes give various options for coding
  operand references
• Addressing modes depend on whether memory or a
  register is being addressed
• A direct 4GB memory address requires 32 bits
• 32 general-purpose registers require just a 5-bit
  address

25
Addressing modes

• There are several generic addressing modes
• An example of immediate addressing is the BIPUSH
  instruction of the IJVM
• The byte of data is part of the instruction stream

26
Common addressing modes

• Register addressing
• Direct addressing with a register designated
• The data is in the register
• Only 5 bits needed for 32 registers
• Register indirect addressing
• The register contains the memory address of the
  data
• In other words, the register contains a pointer
  to the data
• Only 5 bits are needed to reference a 32-bit
  memory address, assuming 32 registers

27
Common addressing modes

• Indexed addressing
• Like register indirect addressing, except an
  offset is added to the address in the register
• The address consists of the register number
  together with the offset value
• PC-relative addressing
• This is indexed addressing with the PC used as
  the register
• It is often used with branch instructions
• The offset targets a location a fixed distance
  before or behind the current instruction

28
Common addressing modes

• Indexed addressing with autoincrementation
• This is indexed addressing in which the register
  is automatically incremented by an increment
  whenever the mode is used
• It can be used for conveniently stepping through
  a table
• Based-index addressing
• The address is the sum of two registers plus an
  optional offset
• One register might contain the base address of a
  table
• The other might contains an index into the table

29
Common addressing modes

• Stack addressing
• Example is the IJVM
• Branch addressing
• PC-relative addressing is typical
• Register indirect addressing is also convenient
• The register is loaded ahead with the destination

30
Orthogonality

• Orthogonality refers to independence of opcodes
  and addressing modes of operands
• An orthogonal instruction set allows an opcode to
  have operands that use any addressing mode that
  makes sense
• All user registers are equally allowed
• The addressing mode of each operand needs to
  identify itself

31
Orthogonality

• The DEC VAX was a highly-successful architecture
  with an orthogonal instruction set
• Most architectures are far from orthogonal

A simple design for the instruction formats of a
two-address machine
32
A comparison of addressing modes
33
Common ISA instructions

• ISA level instructions usually fall into the
  following groups
• Data movement instructions
• Dyadic operations
• Combine two operations to produce a result
• Monadic operations
• One operand with one result
• Comparisions and conditional branches
• Procedure call instructions
• Loop control
• Input / output
• We have covered Intel 8088 assembly language and
  have seen examples of most of these types of
  instructions
• For additional examples, see text, pp. 375 - 386

34
Levels of I/O support

• The levels of I/O support are . . .
• 1. Programmed I/O with busy wait
• 2. Interrupt-driven I/O
• 3. Direct Memory Access (DMA)
• The first two levels involve only
  single-character transfer
• The last level involves block transfer

35
Programmed I/O with busy wait

• Consider a simple terminal with four 1-byte
  registers
• These are typically used with memory-mapped I/O
• Assume interrupts are not enabled for now

36
Programmed I/O with busy wait

• For input from the keyboard, the leftmost status
  bit (character available) is set by hardware
  whenever the next character arrives
• The program sits in a tight loop, repeatedly
  reading the leftmost status bit
• When the program detects that the bit is set, the
  program reads the keyboard buffer register
• Reading from the buffer register automatically
  clears the status bit

37
Programmed I/O with busy wait

• For output to the screen, the leftmost status bit
  (ready for next character) is set by hardware
  whenever the screen is ready to accept another
  character
• The program sits in a tight loop, repeatedly
  reading the leftmost status bit
• When the program detects that the bit is set, the
  program sends the next character to the display
  buffer
• Writing to the display the buffer register
  automatically clears the status bit

38
Programmed I/O with busy wait

• A sample program that outputs an array of
  characters
• Methods in and out call assembly language
  routines that read the status bit and write to
  the display register

39
Interrupt-driven I/O

• The disadvantage of programmed I/O is that
  program wastes time in the ready loop waiting for
  the device to become ready
• This is called a busy wait loop

40
Interrupt-driven I/O

• Alternative to a busy wait
• Enable the interrupt bits in the status registers
• Start the I/O device and tell it to generate an
  interrupt whenever it becomes ready
• Then go and do something useful
• When the interrupt occurs, the software handling
  the interrupt should read or write the
  appropriate buffer register
• Reading or writing the buffer register clears the
  interrupt
• We will discuss interrupts a little later

41
Direct Memory Access (DMA)

• Handling one interrupt for each character
  transferred generates quite a bit of overhead
• This is not a problem for the keyboard but is
  excessive for block transfer

• The solution is
• Direct Memory
• Access (DMA)

42
Direct Memory Access (DMA)

• DMA transfers a block of data independently from
  the CPU
• Uses cycle stealing
• DMA activation needs . . .
• Base address of the block to be transferred
• The number of bytes to be transferred
• The number of the device involved
• Whether to read or write
• Etc.
• The DMA issues an interrupt when done

43
Traps and interrupts

• An interrupt causes an unscheduled hardware
  implemented call to an interrupt handler method
  associated with the cause of the interrupt
• Cause
• Some asynchronous external event
• For example, I/O completion by DMA controller
• When it is done, the interrupt handler returns
  control to the interrupted program

Note In Section 5.6, we will only cover
subsections 5.6.4 (Traps) and 5.6.5
(Interrupts), pp. 404 - 408
44
Traps and interrupts

• The interrupted program must have all state
  information . . .
• Saved when interrupted
• Restored with the return
• This includes the PC, registers, local variables,
  etc.
• The interrupted program should be unaware that
  the interrupt occurred
• This is called transparency

45
Traps and interrupts

• A trap . . .
• Is an internal interrupt caused by execution of
  an instruction
• E.g., division by 0, overflow, illegal opcode,
  protection violation
• Causes a trap handler to run
• Is usually fatal
• Is synchronous
• If you run the program again, the trap will occur
  in the same place
• This is not so with an interrupt

46
Traps and interrupts

• An interrupt automatically causes a transfer to
  an interrupt handler
• This is facilitated by an interrupt vector
• This is an integer put on the bus by the device
  causing the interrupt
• When responding to the interrupt, the processor
  uses this integer to index into a table giving
  entry points for the various interrupt handlers
• As with a method call, the interrupted programs
  state information is automatically saved and the
  PC is loaded with the entry point of the
  interrupt handler

47
Interrupt details

• Read over the details of interrupt activity
  involved with output of a line of characters to a
  terminal
• HARDWARE ACTIONS on page 405
• SOFTWARE ACTIONS on page 406
• The characters are first placed in a buffer
  pointed to by ptr and the count of the number of
  characters is placed in integer variable count

48
Interrupts and priority

• Traps and interrupts may themselves be
  interrupted
• This resembles nested method calls
• Priority
• Each interrupt has a priority level
• The assigned level is related to the
  time-critical nature of the event causing the
  interrupt
• The interrupt handler for an interrupt may be
  interrupted only by a higher-priority interrupt
• The priority of the currently running program or
  interrupt handler is always available in the PSW

49
Multiple interrupt example