CPU Architectures

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CPU Architectures
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The von Neumann Cycle
pc 0 do instruction memorypc
decode(instruction) fetch(operands)
execute() store(results) while
(instruction ! halt)
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Accumulator Architecture
RAM
MAR
ALU
Address Bus
Accumulator
Data Bus
MDR
CPU
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Example of Accumulator Machine

• EDSAC first stored program computer,
  Cambridge University, 1949 (Wilkes)

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Stack Architecture
RAM
MAR
ALU
Address Bus
Stack
MDR
Data Bus
CPU
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Examples of Stack Architecture

• HP 15C Calculator
• Java Virtual Machine

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Load/Store Architecture
RAM
MAR
ALU
Address Bus
Data Bus
MDR
CPU
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Examples of Load/Store Architecture

• PC
• SPARC
• IBM Mainframes
• Almost all other types of computers

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Typical SPARC program code
save sp, -96, sp mov 3, l0
mov 11, l1 add l0, l1, l2
mov 7, l3 sub l0, l3, l4 smul
l2, l3, l1 mov 1, l2 add l0,
l2, l2 sdiv l1, l2, o1
! This code evaluates the ! polynomial ! (x
11)(x 7)/(x 1)
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SPARC Architecture

• CPU Instruction Set Architecture (ISA) derived
  from a RISC lineage.
• Allows for a wide variety of chip and system
  implementations.
• Designed for optimizing compilers and high
  execution rate.
• Easily pipelined.

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SPARC Features

• 32-bit address space
• Only three basic instruction formats
• Large windowed register file
• Delayed transfer of control