The Physical Design Cycle

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The Physical Design Cycle

• Baidurya Chatterjee

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Why Physical Design ?

• The chip design cycle may be viewed as the
  transformation of HDL code to layout data in
  physical design.
• In order to fabricate a VLSI chip, it needs to be
  represented as several layers of planar geometric
  elements or polygons.
• These elements are generally Manhattan structures
  without any overlap in the same layer and a great
  degree of precision because this is the data that
  ultimately goes to silicon.
• Symbolic database converted to polygon database
  before fabrication.

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Flow Diagram
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What is Backend ?

• Physical Design
• Floorplanning Architects job
• Placement Builders job
• Routing Electrician Job
• Though all of this is at the sub-micron level ?

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So what is Partitioning ?
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Partitioning of a Circuit
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Why Partition ?

• Ask Lord Curzon ?
• It is the most logical way of solving problems of
  high complexities and thus finds great use in
  VLSI chip designs.

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Partitioning

• Efficient designing of any complex system
  involves the decomposition of the same into
  smaller subsystems.
• Subsequently each subsystem can be designed in
  parallel which would speed by the design process.
  This decomposition is known as Partitioning.

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Issues

• Decomposition must be carried out in such a way
  so that the functionality of the system is
  unchanged.
• A proper interface specification should be
  generated which is used to connect the subsystems
  so obtained and minimize the number of
  interconnections between them.
• The size of each partition is also a
  consideration.
• The partitioning process should be simple and
  efficient so that it consumes a fraction of the
  total design time.

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Circuit Representation

• Netlist
• Gates A, B, C, D
• Nets A,B,C, B,D, C,D
• Hypergraph
• Vertices A, B, C, D
• Hyperedges A,B,C, B,D, C,D
• Vertex label Gate size/area
• Hyperedge label
• Importance of net (weight)

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Problem Formulation

• The input to the partitioning problem is a set of
  components and a netlist. The output is a set of
  sub-circuits.
• Formally it may be expressed as
• A hypergrapgh G(V,E) representing a partitioning
  problem may be represented as follows
• V v1,v2,,vn be the set of vertices
• E e1,e2,.,en be the set of hyper edges
• where the vertices represent the components and
  there is a hyperedge joining the vertices
  whenever the components corresponding to these
  vertices need to be connected.
• Thus the partitioning problem is to partition V
  into V1,V2,Vn such that v1
• The graph partitioning problem is NP-complete.

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Objectives

• Interconnections between the partitions are
  minimized.
• Delay due to partitioning is minimized as the
  delay between blocks is larger than within a
  block.
• Number of terminals
• Area of each partition should be reasonable.
• Number of partitions must be optimal which
  affects the above mentioned parameters.

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Classification of Partitioning Problems

• Classified differently depending on the nature of
  design style being used such as standard cell,
  full custom and gate array.
• The min-cut problem is NP-complete and so is the
  general partitioning. Variety of heuristic
  approaches have been developed primarily
  classified as
• Based on the nature of the input
• Constructive
• Iterative
• Nature of the algorithms
• Deterministic
• Probabilistic

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• On the basis of partitioning technique
• Group Migration Algorithms
• Simulated Annealing
• Other approaches

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Group Migration Algorithms

• Belong to the class of iterative improvement
  algorithms. They start with an initial partition,
  and then improve on it.
• Kernighan-Lin
• Fiduccia-Mattheyeses

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Kernighan-Lin Algorithm

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The Algorithm
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Computing the gain
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Example
Initial Partition
Final Partition
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Continued
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Drawbacks of the K-L Algorithm
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Kernighan-Lin
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Other approaches

• They include the FM algorithm and other commonly
  used evolutionary algorithm based approaches such
  as simulated annealing etc.
• We obtain a set of sub-circuits and their
  interconnections and this forms the input to the
  floor planning problem.

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Simulated Annealing

• Can be mapped as a state space search problem
• Combinatorial optimization problems (like
  partitioning) can be thought as a State Space
  Search Problem.
• A State is just a configuration of the
  combinatorial objects involved.
• The State Space is the set of all possible states
  (configurations).
• There is a cost corresponding to each state.
• A Neighbourhood Structure is also defined (which
  states can one go in one step).
• Search for min/max cost state

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Greedy Algorithms

• A very simple technique for State Space Search
  Problem.
• Start from any state.
• Always move to a neighbor with the min cost
  (assume minimization problem).
• Stop when all neighbors have a higher cost than
  the current state.
• Problem is that it gets stuck at a local
  minimaoften !!

Cost
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Simulated Annealing

• Very general search technique.
• Try to avoid being trapped in local minimum by
  making probabilistic moves.
• Popularize as a heuristic for optimization by
• Kirkpatrick, Gelatt and Vecchi, Optimization by
  Simulated Annealing, Science, 220(4598)498-516,
  May 1983.

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Simulated Annealing

• Inspired by the Annealing Process
• The process of carefully cooling molten metals in
  order to obtain a good crystal structure.
• First, metal is heated to a very high
  temperature.
• Then slowly cooled.
• By cooling at a proper rate, atoms will have an
  increased chance to regain proper crystal
  structure.
• Attaining a min cost state in
  simulated
• annealing is analogous to
  attaining a good
• crystal structure in annealing.

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Simulated Annealing
Drop back
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Basic Idea

• Let t be the initial temperature.
• Repeat
• Repeat
• Pick a neighbor of the current state randomly.
• Let c cost of current state.
• Let c cost of the neighbour picked.
• If c lt c, then move to the neighbour (downhill
  move).
• If c gt c, then move to the neighbour with
  probablility e-(c-c)/t (uphill move).
• Until equilibrium is reached.
• Reduce t according to cooling
  schedule.
• Until Freezing point is reached.

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Floor planning

• Post partitioning the possible shapes of the
  blocks obtained are ascertained area as well as
  the number of terminals are determined.
• The arrangement of blocks on the chip/board is
  done in two phases viz. floor planning and
  placement.
• Floor planning phase consists of placing and
  sizing of blocks and interconnect while the
  placement phase involves assignment of exact
  location to blocks.
• The basic idea here is to place the blocks in
  such a way and also the terminals so that the
  routing area is minimized.

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Types of Floorplans

• Slicible
• One that can be obtained by repeatedly
  subdividing rectangles horizontally or
  vertically.
• Non-slicible
• One that need not be obtained by subdividing
  alone.

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Problem Formulation
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Output
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Slicing Tree
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Example
Slicing Tree
Layout