Overview of Trimaran Compiler Research Infrastructure

1
Overview of Trimaran Compiler Research
Infrastructure

• March 27, 2001

Presented By
Anup Gangwar
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Introduction

• The Architecture DSE Problem
• Motivation Compiler Research and DSE
• Trimaran for Compiler Research in ILP
  Architectures
• Need for Retargetable Compilers (RC)

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The Trimaran System
User C-Code (or Std. Benchmarks)
Elcor IMPACT (Retargetable Compiler)
HM-Des (Machine Description)
Generate/Modify Hardware Description
Executable Code (Binary for Host Platform)
Perf. Monitor (Run-Time Statistics)
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Trimaran Capabilities

• Supports HPL-PlayDoh Type Architectures
• Ability To Add New Functional Units
• Possibility To Add New Code Optimizers
• Possibility To Add New Performance Monitors
• RC Supports Most of ANSI C

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The Machine Description Language

• Format Section
• Resource Usage Section
• Latency Section
• Operation Section
• Register Section

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Format Section

• Field Type
• Section Field_Type
• REG()
• NULL()
• ialu ()
• Operation Format
• Section Operation_Format
• OF_Std1 ( dest(REG) src(REG REG) )
• OF_Std3 ( dest(REG) src(REG) )
• RU_mem_t0_1 ( use ( mem ) time ( 0 1 ) )

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Resource Usage Section

• Resource
• Section Resource
• Slot0 () // Instruction issue slots
• Slot1 ()
• Resource Usage
• Section Resource_Usage
• RU_Slot0 ( use ( Slot0 ) time ( 0 ) )
• RU_Slot1 ( use ( Slot1 ) time( 1 ) )

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Resource Usage Section

• Resource Unit
• Section Resource_Unit
• ialu_unit ( use ( RU_ialu ) )
• ibr_unit ( use ( RU_ialu ) )
• Table Option
• Section Table_Option
• any_iissue ( one_of( RU_slot0 RU_slot1 ) )
• any_fissue( one_of( fissue0_unit fissue1_unit )
  )

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Resource Usage Section

• Reservation Table
• Section Reservation Table
• RT_IAlu ( use ( any_iissue ialu_unit ) )
• RT_FPAlu ( use ( any_fissue falu_unit ) )

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Latency Information

• Operand Latency
• Section Operand_Latency
• d1 ( time ( 1 ) )
• d2 ( time ( 3 ) )
• x ( time ( ) ) //When operand is not a
  register
• Operation Latency
• Section Operation_Latency
• OL_Lat1 ( dest( d1 x ) src( s0 s0 s0 s0 )
• // Control and other latency information
• )

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Operation Information

• Scheduling Alternatives
• Section Scheduling_Alternatives
• ALT_FMul2 ( format ( OF_Std1 ) resv( RT_FPMul2
  ) latency ( OL_Lat2 ) )
• ALT_FMul3 ( format ( OF_Std1 ) resv( RT_FPMul3
  ) latency ( OL_Lat3 ) )
• Operation
• Section Operation
• OP_MUL_F ( alt ( ALT_FMul2 ALT_FMul3 ) )
• OP_MUL_F2 ( alt ( ALT_FMul2 ALT_FMul3 ) )

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Register Information

• Register
• Section Register
• fr1 ( )
• fr1R ( overlaps ( fr1 ) )
• Register Classes
• Section Register_Class
• callee( )
• reserved( )

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Demonstration of Trimaran

• Study The Effect of Variation of No. of FUs
• First Architecture
• Integer Units - 4
• Float Units - 2
• Memory Units - 2
• Second Architecture
• Integer Units - 1
• Float Units - 1
• Memory Units - 1

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Dynamic Total Compute Cycles
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Dynamic Total Operations
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Dynamic Average Issue Width
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For More Information

• http//www.trimaran.org
• http//www.crhc.uiuc.edu/IMPACT
• http//cs.nyu.edu/react-ilp
• Intranet http//10.20.10.28080