ECE 353 Introduction to Microprocessor Systems

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ECE 353Introduction to Microprocessor Systems
Week 10

• Michael G. Morrow, P.E.

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Topics

• ADuC7026 External Memory Interface
• Implementation
• Demultipexing
• Bus Timing
• Bus cycle timing modification
• Wait states and more
• Assessing timing compatibility

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Basic System Bus Operation

• Address
• Unidirectional from CPU
• Data
• Bidirectional
• Control
• /RS or /RD output from CPU
• Indicates a read operation in progress
• /WS or /WR output from CPU
• Indicates a write operation in progress
• /WAIT or /READY input to CPU
• Used by external device to signal that it is not
  able to complete transfer yet (not present on
  ADuC7026)

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ADuC7026 Bus Operation

• The ADuC7026 external memory interface consists
  of
• 16-bit multiplexed address/data bus (AD150)
• High address bit for 8-bit operation (A16)
• Read and write strobes (/RS, /WS)
• Memory select signals (/MS30)
• Internal decodes of upper 15 bits of address
• Byte enables (/BHE, /BLE)
• Demultiplexing control signal (AE)
• There is no WAIT/READY signal
• Basic Read Cycle Sequence at Bus Level
• Diagram
• Basic Write Cycle Sequence at Bus Level
• Diagram

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ADuC7026 Demultiplexing

• Multiplexed Signal Timing
• Read Cycle
• Dealing with a multiplexed bus
• Demultiplexing by the device
• Demultiplexing logic to create an address bus
• Implementation
• Devices
• Connections
• AE timing

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SRAM Timing Compatibility

• In order to properly read and write the device,
  we need to ensure that the processor-to-memory
  interface is compatible with the memory device.
• This is accomplished by analyzing the timing for
  all relevant parameters, and ensuring that the
  operation can be completed successfully.
• We will work through the read cycle analysis for
  the ADuC7026...

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Assessing Timing Compatibility

• Need to know whether CPU could operate with the
  tAA for given device. (read cycle)
• We designate a CPU characteristic tAVDV, which is
  the delay from
• When the address becomes valid at the CPU
• Until the data must be driven back to CPU
• This establishes an upper bound on tAA
• tAA lt tAVDV
• Read cycle parameters
• Read cycle timing control

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System Timing Compatibility

• Need to account for all delays in a system to
  assess timing compatibility.
• Consider this system.
• Analyze the read timing with regard to
• tAA address access time
• tACS chip enable to valid data
• tOE output enable to valid data
• tDF output hold/float time
• Read cycle timing control

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ADuC7026 External Memory Interface Configuration

• The external memory interface supports four
  independently configured memory regions, each of
  which is 128kB in size.
• In order to use the external memory interface, we
  need to
• Configure the required pins (GPxCON)
• Enable the external interface (XMCFG0 1)
• Configure for bus width and enable the region
  (XMxCON)
• Configure for the desired bus timing (XMxPAR)

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ADuC7026 XMxCON

• The XMxCON registers configure the bus width and
  enable the interface for the respective memory
  region. Only D10 are used.
• XM0CON ? 0x10000000-0x1001FFFF
• XM1CON ? 0x20000000-0x2001FFFF
• XM2CON ? 0x30000000-0x3001FFFF
• XM3CON ? 0x40000000-0x4001FFFF

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ADuC7026 XMxPAR
Write cycle timing control Read cycle timing
control

• The XMxPAR MMR configures the bus timing for a
  region
• 0x70FF at reset
• 1412 AE extend
• 9 implements bus turn-around
• 8 provides additional hold time
• 74,30 extend write/read strobes

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System Timing Compatibility

• Consider again the system.
• Analyzing write cycle timing.
• SRAM write characteristics
• tWC
• tAS, tAW, tCW
• tWR
• tWDS, tWDH
• Write cycle controls

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Timing Wrap-Up

• Device characteristics are just part of the total
  timing analysis picture
• Line/device capacitive loading and driver slew
  rates
• Transmission line effects and parasitic reactance
• Impedance mismatch and reflections
• Skew and physical/electrical trace length
  mismatch
• Signal integrity
• Ensuring that signals are correct in spite of all
  of the above issues and mutual coupling effects

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Wrapping Up

• Complete Pre-Quiz 5 by the start of class on
  Monday, November 9th
• Homework 5 will be due on Wednesday, November
  11th
• Reading for next week (interrupts and exceptions)
• Textbook chapter 10
• ADuC 74-75
• ARM7 2.8-2.10

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Basic Read Cycle
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Basic Write Cycle
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Read Cycle Parameters
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Write Cycle Parameters
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Read Cycle Controls
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Write Cycle Controls
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16-Bit Memory System
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Ref

• Ref