Extended VHDL

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Extended VHDL

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

• Variables
• Example
• process(inputs)
• variable var std_logic_vector(7 downto 0)
• Begin
• --logic
• var input1 input2
• end process
• Not synthesizable
• Immediate updatable

• Types
• Example
• type myType is record
• en std_logic
• min std_logic_vector(7 downto 0)
• max std_logic_vector(7 downto 0)
• end record
• signal r myType
• r.en lt 1
• r.max lt r.min

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Pipeline

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

• Synchronous design
• Asynchronous logic between synchronous latches

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2 process method

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

• Synchronous and asynchronous process
• Synchronous only copying signals
• Asynchronous all other logic

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2 process structure

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

sequential process(clk) begin if (clk'event
and clk'1') then r lt r_in end if end
process
combinational process(data_in, r) variable tmp
myType begin --logic e.g. tmp.en
1 r_in lt tmp --outputs e.g. output lt
r.en end process
type myType is record --all latched signals end
record signal r, r_in myType
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2 process advantages

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

• Only two processes
• Easy to simulate and synthesize
• Easy to understand design
• No effect on implemented logic
• Easy to change design

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State machine introduction

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

• All process can be described by state machines
• Mathematically complete
• State machines can greatly simplify some
  processes
• Easy to understand, adapt

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State machines

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

• Moore outputs depend on current state
• Mealy outputs depend on current state AND inputs

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State machine example

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

architecture arch of design is type state is
(p0,p1,,p9) signal toestand
state begin process(clk) begin if (clk'EVENT
and clk'1') then case toestand is when p0
gt output lt "0000" toestandltp1 w
hen p1 gt output lt "0001" if
(input1) then toestandltp2 else
toestandltp9 end if when others
gt end case end if end
process end arch
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Demonstration

• Extended VHDL
• Pipeline
• 2 process method
• 2 process structure
• 2 process advantages
• State machine introduction
• State machines
• State machine example
• Demon-stration

• Demonstration VHDL projects

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