Workshop on Testing of High Resolution Mixed Signal Interfaces

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Workshop on Testing of High Resolution Mixed
Signal Interfaces

• Held in conjunction with the DATE2005
  ConferenceFriday 11th March 2005Munich, Germany

Sponsored by Fr. V-IST project 34283 Testability
of Analogue Macrocells Embedded in
System-on-Chip TAMES-2
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Progresses in embedded high-resolution converters
industrial test techniques

• Christophe Gaillard
• Dolphin Integration, France

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Summary

• Part I TAMES2 Project Overview
• Part II Innovative test techniques
• Part III Discussion

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Part I Tames2 Project Overview

• Partners, Key Figures
• Description of Works
• Silicon Demonstrators

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KEY FIGURES, PARTNERS

• 2.5 Years Project Duration
• 4 Partners (2 academic, 2 industrial)

DOLPHIN Integration
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Objectives

• The work will respond to three key industrial
  demands
• Test cost reduction through minimization of test
  time and test development cost
• Improvements in test coverage and outgoing
  quality, to address the industrial trend for
  higher quality product at lower cost.
• Development of test reuse concepts and
  integration of the associated advances in test
  engineering into the design flow for new
  interface designs in SoC applications.

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Description of the work main steps

• The work to be carried out to achieve the
  advances proposed in converter test engineering
  will be driven by industrial users requirements.
• The main steps of the TAMES-2 project are
  proposed in the following slides

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Study of the requirements for industrial
mixed-signal test

• A detailed review of test strategies for HR
  converters has been carried out.
• Reference test plans have been worked out
• Circuit level failure mode analysis, correlation
  with design specification
• Specification testing effectiveness

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Definition of suitable innovative Test Techniques

• Innovative Test Techniques have been studied
  using both BIST and black box approaches
• Decision Matrix a tool for performance
  evaluation and comparison was developed to
  provide a rational metrics

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Validation of the objectives through the design
of industrial SIP

• an audio codec and an automotive interface, both
  representing macrocells for use in much larger
  SoC designs and having complementary test
  requirements.
• this design includes specification and
  architecture of the SIP blocks, development of
  robust schematics for the analogue part
• implementation of DfT techniques and layout in
  advanced CMOS processes

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Use Plan

• Use of the SIP blocks
• by AMI Semiconductors
• by Dolphin through inclusion in its SIP catalogue
• Packaging of the test techniques to allow usage
  by SoC integrators

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Dissemination of results

• Result dissemination through academic courses and
  international conferences
• Web site
• http//www.imse.cnm.es/tames2

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Part II Innovative Test Techniques

• Choice for Silicon demonstrators
• Alternatives to FFT analysis
• Alternatives to histogram testing
• Bist solution, on-chip test support
• Re-usability

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Design and fabrication of test chips including
the two SIP blocks
95 dB Stereo ADC PGA
45 kgates Digital filters and interfaces spRAM
95 dB Stereo DAC speaker drivers
CODEC Demonstrator Test chip 25 mm2 (Dolphin
Integration)
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Sensor Interface Silicon demonstrator (IMSE)

• Automotive sensor IF Specifications
• Resolution DR 17bit
• SNR-peak gt 100dB
• Digital output rate 40kS/s
• Signal bandwidth Bw 20kHz
• Signal range 140dBV (Vref 2V)
• Temperature range (- 40,175)ºC
• Minimum power consumption
• Tech. 3.3V-0.35mm CMOS (I3T80)

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Choice of Silicon Demonstrators

• The choice of silicon demonstrators was done to
  cover different, an complementary, test
  requirements
• The HR sensor interface addresses high
  reliability automotive market, requires static
  test measurements (INL, DNL) based on sine wave
  histogram
• The High Resolution CODEC addresses consumer
  market, and requires dynamic testing (SNR, THD)
  based on FFT processing.

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Challenge of High Resolution Testing in brief

• Test of high resolution analog IP is one of the
  major hurdle to mixed signal SoC development.
• Above 16 bit resolution
• Data rate in the kHz range
• Huge acquisition time
• Require strong tester analog resources for
  stimulus generation
• Test coverage
• Processing power
• Test development cost (hardware and software)

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Alternatives to histogram test

• FFT-INL
• Based on the application of the FFT transform
• Wavelet
• Based on the application of the Hilbert transform
• Aimed to reduce the test time by minimising the
  number of samples needed to perform the INL
  measurement

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Alternatives to FFT-based dynamic testing

• Embedded distortion meter instrument
• On chip Digital filtering (notch filter)
• RMS power computation for SNR and THDN
  measurements
• Possibly BIST with on chip stimulus generation
• Other transforms
• Two transformation techniques, namely discrete
  sine transform and arithmetic Fourier transform
  implementing DFT with less algorithmic complexity
  than FFT radix 2.
• Walsh SNR testing using on chip TSG

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Conclusions

• Efficiency of test techniques proven with silicon
  demonstrators
• Improved test plans are proposed using the new
  test techniques
• High re-use potential for mixed signal SoC with
  partial on-chip test support.
• Test development facilitated by high level models
  and IP supplier support.

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Thats it
any questions ?
Thank You!