Design Goal

1
Design Goal
TEAM W3Digital Voice Processor 525
Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim
(W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5)
Design Manager Abhishek Jajoo
Date 4/12/2006 Top Level Layout

• Design an Analog-to-Digital Conversion chip to
  meet demands of high quality voice applications
  such as Digital Telephony, Digital Hearing Aids
  and VOIP.

2
Status

• Project chosen 16 bit Delta-Sigma ADC - Basic
  specs defined
• Architecture
• Schematic
• Floor Planning
• Revised Layout Dimensions
• Layout Progress
• Top Level Analog
• Delta/Sigma Modulator
• Low Pass Filter DRC, LVS, Simulated
• Top Level Digital
• PII DRC, LVS, Simulated
• Sinc Filter DRC, LVS, Simulated
• Clock Divider DRC, LVS, Simulated
• Simulation / Verification
• All Digital Modules Verified
• All Analog Modules Verified
• Overall/Top Verified
• Optimized Layout
• Analog Components

3
Design Decisions

• Trade area from capacitor to resistor
• Widening VDD and GND lines for sinc and pii
  function

4
Analog Progress

• Delta/Sigma Modulator
• Completed DRC/LVS of Module
• Completed Schematic/Layout Verification
• Working on Analog Top Level Layout
• Working on Optimizing Module Layout

5
Modulator -schematic
6
Schematic Simulation
7
Extracted Simulation
8
Schematic
Extracted
9
Effects of Mismatch on ?S
Matched RC and Diff Pair Transistors
Increased 10 Diff Pair Size
Decreased 10 Diff Pair Size
Only 10 RC Mismatch
10
Analog Mismatch
11
Digital Progress

• Working on widening the lines
• gtgt mostly complete in the sinc filter and pii
  function
• Making the bitslices of the sinc filter tighter

12
PII Zoom - Layout
13
PII Function - new Layout
14
Preliminary Top Level - Layout
15
Layout Power/Timing
Module Power Power Area T-Count
Module Schematic Extracted Area T-Count
Clock Divider 6.534mW_at_20KHz 7.138mW_at_20KHz 1,740um2 334
2nd Order Sinc Filter 14.2mW_at_5.12MHz 20KHz 15.33mW_at_5.12MHz 20KHz 17,967um2 3296
PII Function 260.7nW_at_20KHz 292.0nW_at_20KHz 17,955um2 2782
Decimator (Top Digital) 20.99mW 22.76mW 45,474um2 6412

Analog Op-Amps/Modulator 162uW (Op Amp Power) 162uW (Op Amp Power) -- 20
Low Pass Filter Max 327.6uW Max 327.6uW 59,899um2 0
Modulator (Top Analog) Max 837.4uW Max 837.4uW 137,764um2 6,432
16
Problems and Questions

• Extracted comparator can't seem to handle the
  load of the extracted D flip flop
• The best way to debug extracted views?