12' Design of Simple Processor

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12. Design of Simple Processor

• Processor organization
• Executing instructions
• Processor implementation using VHDL

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Tri-State Buffers

• A tri-state buffer has a data input and a control
  input.
• when control input is asserted, output equals
  input
• when control input is not asserted, output is
  disconnected from input - called high impedance
  state

• Tri-state buffers, can be used to build
  distributed multiplexors.
• Shared outputs are called buses.
• Also allows single wire to be used as data input
  and output.

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Data Transfer Using Buses
Q
D
Q
Register 1
D
Q
D
Register 2
Register 3
LD
LD
LD

• A bus is a shared set of wires used to transfer
  data among any of several sources/destinations.
• Data transfers involve
• enabling source to place data on the bus
• loading data into destination

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Detailed Processor Diagram
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Alternate Processor Diagram
IAR
IREG
ACC
ALU
compare
PC
LD
LD
LD,
OP
LD
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Processing Cycle

• Instruction fetch
• PC used to read word from memory
• PC is incremented
• Instruction decode
• first 4 bits of retrieved instruction are decoded
  to determine what to do
• appropriate circuitry activated
• Instruction execution
• retrieve additional memory words
• write to memory
• modify PC or ACC contents
• may take different amounts of time to complete

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Instruction Execution

• Direct Load
• transfer data from memory to ACC, using low 12
  bits of instruction word as memory address
• requires asserting of memory signals and loading
  ACC
• Conditional branch
• determine if ACC0 (or gt0 or lt0)
• if so, transfer low 12 bits of instruction word
  to PC
• Indirect store
• transfer data from memory to Indirect Address
  Register (IAR) using low 12 bits of instruction
  word as memory address
• transfer data from ACC to memory, using IAR
  contents as address
• requires placing IAR value on address bus and
  asserting signals to perform memory write

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Instruction Fetch
2. Memory contents on Dbus
5. Increment PC
3. Load IREG
1. PC value on Abus
1. mem_en 1
4. mem_en 0
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Add Instruction Execution
2. Memory contents on Dbus
3. ALU adds values
1. IREG value on Abus
4. Load sum into ACC
1. mem_en 1
5. mem_en 0
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Signal Timing for Processor
enable memory for reading
add tick to timing diagrams
PC value on Abus
PC loaded
PC incremented
IREG loaded
ACC loaded
ACC loaded
ACC loaded
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Signal Timing for Processor
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Processor VHDL Specification
entity cpu is port ( clk, reset in
std_logic m_en, m_rw out std_logic
aBus out address dBus inout
word snoopPort out regSet proceed in
std_logic ) end cpu architecture cpuArch of
cpu is type state_type is (reset_state,
fetch, halt, negate,...) signal state
state_type signal tick std_logic_vector(3
downto 0) signal pc address -- program
counter signal iReg word -- instruction
register signal iar address -- indirect
address register signal acc word --
accumulator signal alu word -- alu output
processor state and timing definitions
primary processor registers
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Processor Instruction Decoding

• begin
• snoopPort.pc lt pc snoopPort.iReg lt iReg
• snoopPort.acc lt acc snoopPort.iar lt iar
• alu lt (not acc) x"0001" when state negate
  else
• acc dbus when state add
  else
• acc and dbus when state andd
  else
• (alu'range gt '0')
• process (clk) -- process for events that happen
  on rising edges.
• procedure decode is begin -- Instruction
  decoding.
• case iReg(15 downto 12) is
• when x"0" gt
• if iReg(11 downto 0) x"000" then state lt
  halt
• elsif iReg(11 downto 0) x"001" then state lt
  negate
• else state lt halt
• end if
• when x"1" gt state lt mload
• ...
• when x"d" gt state lt andd

enable snooping on CPU registers
ALU operations
decode instructions
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Processor Instruction Fetch
procedure wrapup is begin -- Do this at end of
every instruction state lt fetch tick lt
x"0" end procedure wrapup begin if
rising_edge(clk) '1' then if reset '1'
then state lt reset_state tick lt
x"0" pc lt (pc'range gt '0') iReg lt
(iReg'range gt '0') acc lt (acc'range gt
'0') iar lt (iar'range gt '0')
else tick lt tick 1 -- advance time by
default case state is when reset_state gt
state lt fetch tick lt x"0" when fetch gt
if tick x"1" then iReg lt dBus end
if if tick x"2" then if
proceed '1' then decode pc lt pc
1 tick lt x"0" else tick
lt x"2" -- hold at end of fetch end
if end if when halt gt tick
lt x"0" -- do nothing when negate gt acc lt
alu wrapupll
last step of every instruction
wait for proceed signal (for single step mode)
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Processor Load/Store
-- store instructions when mload gt
if iReg(11) '0' then -- sign
extension acc lt x"0" ireg(11 downto 0)
else acc lt x"f" ireg(11 downto
0) end if wrapup when dload
gt if tick x"1" then acc lt dBus end
if if tick x"2" then wrapup end
if when iload gt if tick x"1" then
iar lt dBus end if if tick x"4" then acc
lt dBus end if if tick x"5" then wrapup
end if -- store instructions when
dstore gt if tick x"4" then wrapup end
if when istore gt if tick x"1" then
iar lt dBus end if if tick x"7" then
wrapup end if
extend sign on immediate load
load IAR from memory
load ACC from address specified by IAR
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Processor Branch, Arithmetic
-- branch instructions when branch gt
pc lt x"0" iReg(11 downto 0)
wrapup when brZero gt if acc x"0000"
then pcltx"0" iReg(11 downto 0)end
if wrapup when brPos gt if
acc(15) '0' and acc / x"0000" then pc
lt x"0" iReg(11 downto 0) end
if wrapup when brNeg gt if
acc(15) '1' then pcltx"0" iReg(11 downto
0) end if wrapup -- arithmetic and
logic instructions when add andd gt if
tick x"1" then acc lt alu end if if tick
x"2" then wrapup end if when others gt
state lt halt end case end if end
if end process
update PC as appropriate
differentiated only by ALU operation
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Processor Falling Edge Process
process(clk) begin if falling_edge(clk)
then if reset '1' then m_en lt '0' m_rw
lt '1' aBus lt (aBus'range gt 'Z') dBus lt
(dBus'range gt 'Z') else case state
is when fetch gt if tickx"0" then m_en
lt '1' aBus lt pc end if if tickx"2"
then m_en lt '0' aBus lt (aBus'rangegt'Z')
end if when dload add andd
gt if tick x"0" then m_en lt '1'
aBus lt x"0 iReg(11 downto 0) end
if if tick x"2" then m_en lt '0'
aBus lt (aBus'rangegt'Z') end if
when iload gt if tick x"0" then
m_en lt '1' aBus lt x"0" iReg(11 downto
0) end if
synchronized to falling clock edge
use PC to supply address
use IREG to supply address
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Processor Writing to Memory
if tick x"2" then m_en lt '0' aBus
lt (aBus'range gt 'Z') end if if
tick x"3" then m_en lt '1' aBus lt iar end
if if tick x"5" then m_en lt '0'
aBus lt (abus'range gt 'Z') end
if when dstore gt if tick x"0"
then m_en lt '1' aBus lt x"0" iReg(11
downto 0) end if if tick x"1" then
m_rw lt '0' dBus lt acc end if if tick
x"3" then m_rw lt '1' end if if tick
x"4" then m_en lt '0' aBus lt
(abus'range gt 'Z') dBus lt (dBus'rangegt'Z')
end if when istore gt ... when
others gt -- do nothing end case end
if end if end process
use IAR to supply address
drop rw after address is stable
raise rw before removing address
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Processor Simulation
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Processor Simulation
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Processor Simulation
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Processor Simulation
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Processor Timing Simulation
add instruction
adding 1
ACC-1 initially
FF prop. plus chip IO delay
memory delay
addition delay
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Synthesis Report CPU FFs

• HDL Synthesis
  
• Synthesizing Unit ltcpugt.
• Found finite state machine ltFSM_0gt for signal
  ltstategt.
• ----------------------------------------------
  ----------------------
• States 15
  
• ...
  
• ----------------------------------------------
  ----------------------
• Found 1-bit register for signal ltm_engt.
• Found 1-bit register for signal ltm_rwgt.
• ...
• Found 16-bit register for signal ltaccgt (and
  ireg, pc, iar).
• ...
• Found 16-bit register for signal
  ltMtridata_aBusgt created at line 176.
• Found 16-bit register for signal
  ltMtridata_dBusgt created at line 176.
• Found 1-bit register for signal ltMtrien_aBusgt
  created at line 176.
• Found 1-bit register for signal ltMtrien_dBusgt
  created at line 176.
• Found 4-bit register for signal lttickgt.
• Summary
• inferred 1 Finite State Machine(s).

1 hot encoding gives 15 for total of 119 flip
flops
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Support Components in S3 Version
IO block accepts input from switches and puts
output on display IO regs mapped to memory
loader initializes memory shile suspending
operation of other components
single step controller generates proceed signal
that enables instruction execution
debouncer provides clean button transitions
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Loader Specifying Program

• entity loader is port (
• clk, restart in std_logic
• reset, m_en, m_rw out std_logic
• aBus out address
• dBus inout word)
• end loader
• architecture loaderArch of loader is
• -- Update progSize and program to load a
  different program
• constant progSize integer 14 -- number of
  words to load
• type wordArray is array(0 to progSize-1) of word
• constant program wordArray (
• -- Read input values and accumulate sum.
• -- Display current sum. Stop when zero is input
• x"1000", -- 0000 sum 0 (sum stored in
  location x0020)
• x"4020", -- 0001
• x"1001", -- 0002 loop wait for new value in
  input register
• x"dffc", -- 0003
• ...
• x"6002", -- 000c end of loop

controls memory just like processor
constant array holds program
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Loader Timing Control

• signal inst word
• signal tick std_logic_vector(2 downto 0)
• begin
• -- update reset, inst and tick on rising clock
  edges
• process(clk) begin
• if rising_edge(clk) then
• if restart '1' then
• reset lt '1' inst lt (inst'range gt '0')
  tick lt (tick'range gt '0')
• else
• if tick lt 5 then tick lt tick 1 end if
• if tick 4 then
• if inst lt progSize - 1 then
• inst lt inst 1 tick lt (tick'range gt
  '0')
• else
• reset lt '0'
• end if
• end if
• end if
• end if

assert reset output to suspend other components
increment inst until done
drop reset to enable other components
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Loader Writing to Memory

• -- memory operations occur on falling clock
  edges
• process(clk) begin
• if falling_edge(clk) then
• if restart '1' then
• m_en lt '0' m_rw lt '0'
• aBus lt (abus'range gt 'Z')
• dBus lt (dbus'range gt 'Z')
• else
• case int(tick) is
• when 0 gt m_en lt '1' aBus lt inst
• when 1 gt m_rw lt '0' dBus lt
  program(int(inst))
• when 3 gt m_rw lt '1'
• when 4 gt
• m_en lt '0'
• aBus lt (abus'range gt 'Z') dBus lt
  (dBus'range gt 'Z')
• when others gt -- do nothing
• end case
• end if
• end if

write selected instruction
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IO Circuit

• entity ioUnit is port(
• clk, reset in STD_LOGIC
• en, r_w in std_logic
• abus in std_logic_vector(15 downto 0)
• dbus inout std_logic_vector(15 downto 0)
• snoopPort in regSet
• displayModeBtn, loadBtn in std_logic
• swt in std_logic_vector(nSwt-1 downto 0)
• led out std_logic_vector(nLED-1 downto 0)
• an out std_logic_vector(nDig-1 downto 0)
• ssg out std_logic_vector(7 downto 0)
• )
• end ioUnit
• architecture ioArch of ioUnit is
• constant displayCntBits integer 2
  operationMode17
• signal outReg, ledReg word
• signal displayValue word
• signal selDig std_logic_vector(3 downto 0)

regSet is record including all CPU registers
Controls per digit display time
Values output by program
Value being displayed
Digit now being displayed
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IO Circuit 7 Segment Decode

• type displayModeType is
• (outputReg, progCntr, instReg, accumulator,
  iAdrReg)
• signal displayMode displayModeType
• signal prevDisplayModeBtn std_logic
• constant loadDelay integer 8
  operationMode99999992
• signal inCtrlReg, inReg word
• signal loadCntr bigDelay
• signal prevLoadBtn std_logic
• function ssDecode(digit std_logic_vector(3
  downto 0))
• return std_logic_vector is
• -- Seven segment display decoder.
• variable result std_logic_vector(7 downto 0)
• begin
• case digit is
• when x"0" gt result x"c0" -- b"11000000"
• when x"1" gt result x"f9" -- b"11111001"
• ...
• end case

display mode options
min button press needed to load high byte of inReg
function specifying on-off pattern for each hex
digit
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IO Circuit Reset Load Buttons

• begin
• process(clk) begin
• if rising_edge(clk) then
• prevLoadBtn lt loadBtn dbus lt (dbus'range gt
  'Z')
• if reset '1' then ...
• else
• -- time how long the load button is held down
• if loadBtn gt prevLoadBtn then
• loadCntr lt (loadCntr'range gt '0')
• elsif loadBtn '1' then
• if loadCntr / loadDelay then
• loadCntr lt loadCntr 1
• end if
• end if
• -- input data when load button is released
• if loadBtn lt prevLoadBtn then
• if loadCntr / loadDelay then
• inReg(7 downto 0) lt swt inCtrlReg(0) lt
  '1'
• else

reset counter on button press
keep counting up to loadDelay
update inReg based on length of button push
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IO Circuit Memory-Mapped IO

• -- handle memory-mapped IO by program
• if en '1' and r_w '0' then
• case aBus is
• when x"0ffc" gt inCtrlReg lt dBus
• when x"0ffd" gt inReg lt dBus
• when x"0ffe" gt ledReg lt dBus
• when x"0fff" gt outReg lt dBus
• when others gt -- nada
• end case
• elsif en '1' and r_w '1' then
• case aBus is
• when x"0ffc" gt dbus lt inCtrlReg
• when x"0ffd" gt dbus lt inReg
• when x"0ffe" gt dbus lt ledReg
• when x"0fff" gt dbus lt outReg
• when others gt -- nada
• end case
• end if
• end if

mimic memory behavior on selected addresses
on write, update registers
on read, return register values
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IO Circuit 7 Segment Display

• -- Process for showing data on seven segment
  display
• displayProcess
• process (clk, selDig, displayValue, displayCnt)
• begin
• if clk'event and clk '1' then
• displayCnt lt displayCnt 1
• if reset '1' then
• an lt "1111" -- off to start
• displayCnt lt (displayCnt'range gt '0')
• end if
• end if
• case displayCnt(displayCntBits downto
  displayCntBits-1) is
• when "00" gt selDig lt displayValue( 3 downto
  0) an lt "1110"
• when "01" gt selDig lt displayValue( 7 downto
  4) an lt "1101"
• when "10" gt selDig lt displayValue(11 downto
  8) an lt "1011"
• when othersgtselDig lt displayValue(15 downto
  12) an lt "0111"
• end case
• ssg lt ssDecode(selDig)
• end process

displayCnt increments freely when not reset
two bits of displayCnt select displayed digit
displayMode determines displayValue
an determines which physical display digit is
active
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IO Circuit Changing Display Mode

• -- Process for switching among display modes.
• displayModeProcess
• process (clk)
• begin
• if clk'event and clk '1' then
• prevDisplayModeBtn lt displayModeBtn
• if reset '1' then
• displayMode lt outputReg
• elsif displayModeBtn gt prevDisplayModeBtn
  then
• case displayMode is
• when outputReg gt displayMode lt progCntr
• when progCntr gt displayMode lt instReg
• when instReg gt displayMode lt accumulator
• when accumulator gt displayMode lt iAdrReg
• when others gt displayMode lt outputReg
• end case
• end if
• end if
• end process

on button press, advance displayMode
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Things You Should Know

• Tri-state buffers
• what they do, how theyre implemented
• using them to implement buses
• Internal operation of simple processor
• what are the internal components and how do they
  interact?
• what happens as instructions execute?
• when do various events happen during execution?
• VHDL design of simple processor
• specification of processor components
• specifying timing of steps in fetch and
  instruction execution
• controlling memory signals
• IO Circuit
• interaction with running programs
• accepting input and signaling presence of input
• displaying output values and processor registers