Team Frankenstein

1
Team Frankenstein

• 3.6.2003

2
Where We Are

• Done
• Branches w/ and w/o Link
• Cache
• PSR Transfers and Updates
• Preliminary Testing
• In Progress
• Single and Block Data Transfers
• Hazard Detection and Pipeline Stalls
• Interrupts
• Control
• Datapath Construction

3
(No Transcript)
4
Preliminary Testing

• Successfully Tested
• ALUOps (w/ and w/o shift), CLZ, Multiply(w/ and
  w/o accumulate), Register Reads, Register Writes,
  PC Increments, Data Forwarding and Pipeline
  Construction.
• Left Out In This Test
• Cache, Data Hazard Detection, Interrupts,
  Conditional Execution (no PSR), Mode Switching,
  Data Transfers and Swaps, Branches, and Stalls.

5
The Test
LDW R15 0x00000000 LDW R1 0x00000003 LDW R5
0x00000003 LDW R14 0x00000004 LDW R6
0x0000FFFF CLZ R4Rd, R5 ADD R7 R1 R4 ADD
R8 (SLL R14 by R1) R1 CLZ R2Rd, R6 SUB R1
R4 R2 MULT R9 R1 X R5 MULTA R10 ( R9 X R5
) R9 MOV R1 -gtR2 MOV R2 -gtR4 MOV R2 -gtR2
6
Block Data Transfer

• Must break down Block Data Transfer into Single
  Data Transfers
• To do so, we create a Mini Program that runs,
  while stalling the next instruction

7
Same as Single Data

• Need to calculate the offset that will either be
  added or subtracted from the base register (Rn)
  depending on bit U
• Need to decide if we should use the address
  before or after the offset is incorporated
  depending on bit P
• If post, then depending on bit W we need to write
  back into the base register. If pre, we
  automatically write back

8
Block Data Transfer Datapath
9
Data Transfer Mini Program
10
Block Data Transfer
11
Interrupts

• Priority controller
• Entering interrupt is not hard leaving is tricky
• For example,
• SWI --gt IRQ --gt FIQ
• Then you have to drop back out of that,
• FIQ -gt IRQ -gt SWI
• While keeping saving PSR, PC and any state values

12
RESET

• RESET logic on cache done
• Performs 1024 (i.e. 1k worth) of zero writes to
  tags
• Therefore sets values to initial floating values
  in cache

13
Stalls
14
Interrupts

• Generated by executing an instruction
• Software Interrupt (SWI)
• Undefined Interrupt
• Prefetch Abort (invalid instr due to memory)
• Generated by side-effect of instruction
• Data Abort
• Generated externally
• Reset
• IRQ
• FIQ

15
Interrupt Steps

• Save address of next instr in proper R14
• Save CPSR in proper SPSR
• Force mode of CPSR and set I and F bits
• Force PC to fetch interrupt vector address

16
Logical Block Translates Interrupt into Mode
Type of interrupt
FIQ
Reset
etc
IRQ
10000 10001 10010 10011 10111 11011 11111
Forced Mode
17
General Implementation Ideas
Saving instr to R14
Saving CPSR to SPSR
Interrupt
Mode Detect
Reg bank
SPSR Mode
bank
CPSR
SPSR
Mode Detect
Normal addr
addr
MUX
R14 addr
Interrupt
18
General Implementation Ideas
Updating CPSR Mode (also send I and F bits)
Bit 16
/USER?
/Pd
MSR
Intrpt
Interrupt
Loopback
MSR Mode Set
4x1 5 bit MUX Mode bits
Interrupt Set
Unused
Mode Detect
19
Progress

• Working on the multicycle control for previous
  steps
• Abort Interrupt may not be necessary (?)
• Goal to get SWI working first
• Need to look into priority
• Multiple interrupts can occur (interrupt can
  interrupt another interrupt )