Convex Delay Models for Transistor Sizing

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Convex Delay Models for Transistor Sizing

• Mahesh Ketkar, Kishore Kasamsetty, and
• Sachin Sapatnekar
• June 8, 2000

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Outline

• Introduction
• Generalized posynomials
• Delay estimation
• Precharacterization of a set of primitives
• Primitive and gate validation
• Optimization using generalized posynomial models
• Conclusion and future directions

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Introduction
Transistor sizing An important problem in the
development of high performance circuits.
Key Point Quality of solution depends on the
models used for delay and area/power estimation.

• The models used should possess two properties
• Accuracy acceptable in the current deep
  sub-micron (DSM) technologies.
• Suitability for continuous optimization
  techniques,
• and preferably convexity.

Contribution Development of delay models having
acceptable accuracy and convexity properties.
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Convex optimization
For a convex function secant joining two points
lies above the function.
Every Local minimum is also a global minimum.
Use of a convex function avoids any hill climbing
efforts.
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Posynomial functions
Advantage A posynomial function can be converted
to a convex function by the transformation xi
ezi provided xi ? 0.
For Example Elmore delay given by the equation
has the posynomial form.
Refer Fishburn, ICCAD 85
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Existing delay models

• 1. Elmore Delay Model Elmore,JAP48.
  Rubinstein,TCAD83
• Posynomial form , continuous derivative
• Inaccurate for current DSM technologies

• 2. Closed form expressions
• a) Analytical Models Chatzigeorgiou,TCAD99
• Accurate
• Lack of convexity properties
• b) Fitted Models
• May not have continuous derivative
• Lack of convexity properties

• 3. Look-Up table models Rao, ICCD83
• No continuous derivative
• Accuracy depends on the fineness of grid.
• Hence, there is a trade-off between memory
• requirement and accuracy.

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Generalized posynomial
Motivation What we want? Functions with
convexity properties.
Which type of functions have convexity
properties? Posynomials
So, can we extend posynomials and still retain
convexity property? Yes!
What have we got? A class of functions called
generalized posynomials. Posynomials form a
proper subset of the class functions we have
developed.
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Generalized posynomial (Contd.)
A generalized posynomial function is defined
recursively as follows
For Example 4(x2.5y-2z3)0.3(x-0.5y0.4x0.3y3)0
.6 is a first order generalized posynomial.
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Delay estimation
Characterization variables Parameters with
visible effect on delay. Loading capacitance
(CL), Input transition time (?rise), Transistors
on the resistive path (wn1, wn2), Width of the
opposing transistor (wp1).
Generalized posynomial function that lead us to
maximum accuracy has the form
xis characterization variables (CL, ?rise, wn1,
wn2, wp1), Pj,Cij,?ij, and C characterization
constants.
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Posynomial model for full custom design
Generation of posynomial delay models for every
possible gate has two problems 1. Exponential
increase in number of SPICE data points, 2.
Number of delay models may be prohibitively large.

• Solution
• Develop a set of primitives
• Each gate mapped to a primitive.

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Primitives for simple gates
Gates which will be mapped to this primitive. 1.
Inverter (Direct mapping) 2. NAND gate for RISE
delay.
Inverter Primitive (Rising Output)
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Primitives for simple gates (Contd.)
Gates which will be mapped to this primitive. 1.
Inverter (Direct mapping) 2. NOR gate for FALL
delay.
Inverter Primitive (Falling Ouput)
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Primitives for simple gates (Contd.)
Complete set of primitives for simple gates
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Primitives for complex gates
Additional primitives are necessary to accurately
consider internal node capacitances on the
nonconducting transistor chain.
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Primitives for complex gates (Contd)
Additional primitives are necessary to accurately
consider internal node capacitances on the
nonconducting transistor chain.
Primitives for simple gates can be easily
extended to accommodate complex gates.
The nonconducting chain can be replaced by a
single conducting transistor followed by an OFF
(nonconducting) transistor.
If this accuracy is not acceptable more models
can be developed.
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Primitive for sequential element
A static sequential element consists of a set of
pass transistors and a few inverters.
Only one more primitive, channel-connected-compone
nt formed by inverter followed by pass
transistor logic.

• Additional advantage
• Facilitates simultaneous transistor sizing and
  clock
• skew optimization

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Results of primitive development
Why primitive validation? accurately model the
nonlinearities.
Characterization, validation on a disjoint data
set.
Criteria used mean error and deviation.
1. Mean error Acceptable fit Error lt 2
for simple gates
Error lt 8 for complex gates
Example inverter primitive - mean error 0.31.
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Results on primitives (Contd.)
2. Deviation Very small value of deviation is
desirable for predicting behavior of the circuit
accurately. Acceptable deviation lt 5
Example PrimFallB Mean error 1.07. Deviation
2.95.
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Results of gate validation
Gate validation shows 1. we can accurately model
delay of all kinds of static gates, 2.
accuracy of the mapping procedure.
Same two criteria used.
All possible mappings for a gate are
considered. Example NAND3 (Fall Delay) ?
PrimFallA,
PrimFallB,
PrimCoFall NAND3 (Rise Delay) ??
InvRise
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Nand3 validation
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Results of NAND3 validation
To give an example, Consider mapping to
PrimCoFall. Mean Error 1.26. Deviation 2.29.
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Computational Efficacy of the model
A TILOS-like optimizer is used. One transistor on
the critical path is updated in
each iteration. ISCAS85 circuits are optimized
for target delay varying from 70 to 95 of
unsized delay. All the execution times are less
than 10 minutes. Accuracy of delay model is also
tested for the whole circuit. C17 benchmark ?
Optimization ? Comparison with SPICE.
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Conclusion and future work

• Introduced a new class of functions called
  generalized posynomials which are shown to
  possess convexity properties.
• Convex and accurate delay models for various
  kinds of static gates. Errors within acceptable
  limit (lt5).
• Computational efficacy shown by optimizing
  ISCAS85 benchmark circuits.
• Generalized posynomials can be used for modeling
  not only delay but other circuit parameters like
  short-circuit power etc.

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Thank You!