GOSSIP architecture for ATLAS

1
Global chip connections
VDD1.2V
GND0V
I2C High speed up to 3.4Mb/s
serial DCS transceiver bias, thresholds, masks,
etc.
JTAG/ I2C
pixel array
Column logic
Settings data
BCR ECR Clock Trigger
Clock trigger receiver
40MHz clock
trigger
trigger BX number
Serial Data Out, 1Gb/s (copper)
add event Bunch ID
physical data with 8-10 bit coding 1.2Gb/s
trigger _at_ fixed latency (programmable in
chip) clock 40MHz
2
Chip level readout
token, to all columns
trigger
256 columns
readout control
clock trigger BCR ECR
trigger
16 bits readout bus
16 bits readout bus
16 bits readout bus
TTCRX
TriggerEID fifo
clock
clock
8b triggerlatency
256 cells per column
BID counter 11 bits
distribute 8 bits trigger latency, clock,
trigger and token.
24 bits readout bus
event counter
token returnready with event readout
what if the buffer is full ??
token from column to column
T
column buffer
T
T
column buffer
column buffer
add col nr.
24b par gt ser24ns _at_ 1Gb/s
add event ID BID
FIFO
write_busy2
also add start- and end of event.

• Skip column if empty
• pixel to column hand-shake with write-busy1
• column buffer to link FIFO hand-shake with
  write-busy2
• until previous column ready

_at_Token the pixel cell copies its triggered data
in the column buffer. Readout starts automatic
after token comes out of first column. Asynchronou
s process, speed determined by serial data link
(busy as handshake) This means the pixel cell and
column buffer readout faster then 40MHz.
3
Pixel cell functionality
Digital approach
8 bit BunchCrossingID
16 bits readout bus

• additional signals
• reset
• test pulse
• clear buffers ?

Token
BunchClock _at_40MHz
threshold
DAC,4b
tune
Trigger (_at_ fixed latency)
measure readout control logic
hit-low
560 MHz osc.
start
pad
hit flag (trigger FIFO)
hit-high
_at_token
2 hits buffer
pre-load
count
1?
DAC,4b
4b counter
latency counter
4b counter
select
row
latency counter
4b counter
4b counter
mask test
Clear buffer
0?

write data
write_busy

• Time Measurement hit hold
• _at_hit_low count1 560MHz start latency counter
• _at_hit_high count2 560MHz
• _at_ BunchClk stop 560MHz (count1 count2)
• if (latency0) clear buffer flag.
• hit-low hit High 1.56ns res., max 25ns.

if counter 0 free buffer location

• Trigger and Readout
• _at_ trigger write hitFlag in trigger FIFO start
  Lat. counter
• _at_ tokenif (write_busy) hold Tokenif (hitFLAG)
  write value to bus andclear buffer location
• pass token to next pixel cell
• step 1 within 25ns
• step 2 to 3 to next pixel with data within 25ns.

• DCS
• per pixel
• DAC 4bit
• Mask test 2bit
• osc tune 4b
• chip level
• bias DACs 8 8bit
• total data64k 64b.

Token to next pixel
Serial control bus.
8 bias lines.
Average total readout time 5.8us trigger L1
latency 2.5us pixel dead time max 400ns
write_busy
4
Pixel cell functionality
Digital approach
16 bits readout bus
8 bits trigger latency
trigger
token
40MHz
testmask, 2b
write_busy
preamp shaper discriminator
start/stopfast/slow
HIT
start
if hitFlag no write_busy write to bus
clear
16 bits differential bus driver
threshold DAC 8b
trigger FIFO
load
clear
Buffer 0
0?
1?
full flag
hitFlag
hitFlag
hitFlag
hitFlag
latency count
4b LE counter
4b TE counter
load
clear
Buffer 1
full flag
4b LE counter
4b TE counter
0?
1?
latency count
hitFlag
hitFlag
hitFlag
hitFlag
_at_ trigger write 1? result in trigger FIFO. _at_
token check if HitFlag is set, and if so, write
corresponding data to readout bus
560MHz clock
or 560MHz
8bits row nr.
The choice of 1 ore 2 thresholds does make a big
difference in the principle of measurement and
data handling in the pixel cell.Therefore the
original (1 thr.) is kept here.
5
IC Technology (130nm) layer cross section
Technology option 8 Metal layers 6 thin 2 thick
DV-Wire bond Pad
TD
polyimide
nitride
TV
Oxide
LM
Power Vdd
VQ
bus routing
MQ
VL
Power shield GND
M6
V5
bus routing
M5
V4
bus routing
M4
V3
Power shield GND
M3
V2
PC, M1 M2 circuit routing
M2
V1
M1
Salicide
CA
PC
PC
RX
RX
N-WELL
RX
RX